PDF: 09005aef81c737fb/Source: 09005aef81c7379d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF9C64x72.fm - Rev. B 10/07 EN
8 ©2005 Micron Technology, Inc. All rights reserved.
512MB (x72, ECC, SR) 184-Pin DDR VLP RDIMM
Electrical Specifications
IDD Specifications
Table 8: I
DD Specifications and Conditions – 512MB
Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
Parameter/Condition Symbol -40B -335 Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs
changing once every two clock cycles
IDD0 1,395 1,170 mA
Operating one bank active-read-precharge current: BL = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
IDD1 1,665 1,440 mA
Precharge power-down standby current: All device banks idle; Power-down
mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD2P 45 45 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock cycle;
V
IN
=V
REF
for DQ, DM, and DQS
IDD2F 495 405 mA
Active power-down standby current: One device bank active; Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD3P 405 315 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per clock cycle
IDD3N 540 450 mA
Operating burst read current: BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN);
I
OUT =0mA
IDD4R 1,710 1,485 mA
Operating burst write current: BL = 2; Continuous burst writes; One device bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle
IDD4W 1,755 1,575 mA
Auto refresh current
t
REFC =
t
RFC (MIN)
IDD5 3,105 2,610 mA
t
REFC = 7.8125µs
IDD5A 99 90 mA
Self refresh current: CKE ≤ 0.2V
IDD645 45 mA
Operating bank interleave read current: Four device bank interleaving reads;
BL = 4 with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control
inputs change only during active READ or WRITE commands
IDD7 4,050 3,645 mA
