16
AT45DB642
1638FDFLSH09/02
Test Waveforms and Measurement Levels
Output Test Load
AC Characteristics – Parallel Interface
Symbol Parameter Min Max Units
f
SCK1
CLK Frequency 5MHz
f
CAR1
CLK Frequency for Continuous Array Read 3 MHz
f
BARSD1
CLK Frequency for Burst Array Read with Synchronous Delay 5 MHz
t
WH
CLK High Time 80 ns
t
WL
CLK Low Time 80 ns
t
CS
Minimum CS High Time 250 ns
t
CSS
CS Setup Time 250 ns
t
CSH
CS Hold Time 250 ns
t
CSB
CS High to RDY/BUSY Low 150 ns
t
SU
Data In Setup Time 75 ns
t
H
Data In Hold Time 25 ns
t
HO
Output Hold Time 0 ns
t
DIS
Output Disable Time 55 ns
t
V
Output Valid 70 ns
t
XFR
Page to Buffer Transfer/Compare Time 700 µs
t
EP
Page Erase and Programming Time 20 ms
t
P
Page Programming Time 14 ms
t
PE
Page Erase Time 8ms
t
BE
Block Erase Time 12 ms
t
RST
RESET Pulse Width 10 µs
t
REC
RESET Recovery Time 1 µs
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
2.0
0.8
2.4V
tR, tF < 3 ns (10% to 90%)
DEVICE
UNDER
TEST
30 pF
17
AT45DB642
1638FDFLSH09/02
AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK/CLK signal
being low when CS
makes a high-to-low transition, and Waveform 2 shows the SCK/CLK sig-
nal being high when CS
makes a high-to-low transition. Both waveforms show valid timing
diagrams. The setup and hold times for the input signals (SI or I/O7-I/O0) are referenced to the
low-to-high transition on the SCK/CLK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows
timing that is compatible with SPI Mode 3.
Waveform 1
Inactive Clock
Polarity Low and
SPI Mode 0
Waveform 2
Inactive Clock
Polarity High and
SPI Mode 3
CS
SCK/CLK
SI or I/O7 - I/O0
(INPUT)
SO or I/O7 - I/O0
(OUTPUT)
tCSS
VALID IN
tHtSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE
VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK/CLK
SO or I/O7 - I/O0
(OUTPUT)
tCSS
VALID IN
tHtSU
tWL tWH tCSH
tCS
tV
HIGH Z
VALID OUT
tHO tDIS
HIGH IMPEDANCE
SI or I/O7 - I/O0
(INPUT)
18
AT45DB642
1638FDFLSH09/02
Reset Timing (Inactive Clock Polarity Low Shown)
Note: The CS signal should be in the high state before the RESET signal is deasserted.
Serial/Parallel Interface Timing
Command Sequence for Read/Write Operations (Except Status Register Read)
CS
SCK/CLK
RESET
SO or I/O7 - I/O0
(OUTPUT)
HIGH IMPEDANCE HIGH IMPEDANCE
SI or I/O7 - I/O0
(INPUT)
tRST
tREC tCSS
CS
SER/PAR
t
SPH
t
SPS
SI or I/O7 - I/O0
(INPUT)
CMD 8 bits
8 bits
8 bits
MSB
Page Address
(PA12 - PA0)
Byte/Buffer Address
(BA10 - BA0/BFA10 - BFA0)
LSBX X X X X X X X X X X X X X X X
X X X X X X X X

AT45DB642-TC

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 64M bit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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