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ADG633YRUZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ADG633 Data Sheet
Rev. B | Page 12 of 16
TEST CIRCUITS
I
DS
V1
S
D
V
S
R
ON
= V1/I
DS
03275-020
Figure 20. On Resistance
S
D
V
S
V
D
I
S(OFF)
I
D(OFF)
A
A
03275-021
Figure 21. Source Off Leakage
S
D
V
D
I
D(ON)
A
NC
NC = NO CONNECT
03275-022
Figure 22. Drain Off Leakage
S1A
D
V
S
V
D
S1B
GND
EN
A
I
D(ON)
V
DD
V
SS
V
DD
V
SS
03275-023
Figure 23. Channel On Leakage
EN
90%
90%
50%
50%
V
OUT
ADDRESS
DRIVE (V
IN
)
t
TRANSITION
t
TRANSITION
3V
0V
V
DD
V
SS
V
S1A
V
OUT
V
IN
A2
A1
A0
GND
S1A
S1B
D
ADG633
V
DD
V
SS
50Ω
R
L
300Ω
0.1µF 0.1µF
C
L
35pF
V
S1B
03275-024
Figure 24. Transition Time, t
TRANSITION
EN
t
BBM
3V
ADDRESS
DRIVE (V
IN
)
V
OUT
0V
V
DD
V
SS
V
S
V
OUT
V
IN
A2
A1
A0
GND
S1A
S1B
D1
ADG633
80%80%
V
DD
V
SS
50Ω
R
L
300Ω
C
L
35pF
0.1µF 0.1µF
03275-025
Figure 25. Break-Before-Make Delay, t
BBM
Data Sheet ADG633
Rev. B | Page 13 of 16
EN
0.1µF0.1µF
V
S
V
OUT
50Ω
A2
A1
A0
GND
S1A
S1B
D1
V
IN
ADG633
R
L
300Ω
C
L
35pF
V
SS
V
DD
V
SS
V
DD
0.9V
OUT
50% 50%
3V
0V
V
OUT
0V
ENABLE
DRIVE (VIN)
OUTPUT
0.9V
OUT
t
OFF
(EN)
t
ON
(EN)
03275-026
Figure 26. Enable Delay, t
ON
(
EN
), t
OFF
(
EN
)
A2
A1
A0
GND
D
ADG633
S
V
OUT
V
DD
V
SS
V
DD
V
SS
V
S
V
IN
R
S
C
L
1nF
EN
3V
0V
V
OUT
LOGIC INPUT
(V
IN
)
Q
INJ
= C
L
× ΔV
OUT
ΔV
OUT
03275-027
Figure 27. Charge Injection
V
DD
V
SS
V
DD
V
SS
EN
A2
A1
A0
GND
S
D
50Ω
V
OUT
V
S
LOGIC 1
0.1µF
0.1µF
NETWORK
ANALYZER
50Ω
R
L
50Ω
OFF ISOLATION = 20 log
V
OUT
V
S
03275-028
Figure 28. Off Isolation
V
DD
V
SS
V
DD
V
SS
EN
A2
A1
A0
GND
S
D
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
R
L
50Ω
V
OUT
50Ω
V
S
0.1µF
0.1µF
NETWORK
ANALYZER
03275-029
Figure 29. Bandwidth
EN
A2
A1
A0
GND
SA
DA
0.1µF
V
OUT
DB
50Ω
V
S
ADG633
CROSSTALK = 20 log
V
OUT
V
S
0.1µF
R
L
50Ω
NETWORK
ANALYZER
NETWORK
ANALYZER
50Ω
V
DD
V
SS
V
DD
V
SS
03275-030
Figure 30. Channel-to-Channel Crosstalk
ADG633 Data Sheet
Rev. B | Page 14 of 16
OUTLINE DIMENSIONS
16
9
8
1
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 31. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
2.25
2.10 SQ
1.95
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
0.70
0.60
0.50
SEATING
PLANE
0.05 MAX
0.02 NOM
0.203 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
04-15-2016-A
PKG-004025/5112
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
EXPOSED
PAD
Figure 32. 16-Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-23)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
ADG633YRU
−40°C to +125°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
RU-16
ADG633YRU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG633YRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG633YRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG633YCPZ −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23
ADG633YCPZ-REEL7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23
1
Z = RoHS Compliant Part.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADG633YRUZ-REEL7

Mfr. #:
Buy ADG633YRUZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs 90dB 52 Ohm 580MHz CMOS Triple SPDT
Lifecycle:
New from this manufacturer.
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