Data Sheet ADG633
Rev. B | Page 3 of 16
SPECIFICATIONS
DUAL-SUPPLY OPERATION
V
DD
= + 5 V, V
SS
= −5 V, GND = 0 V, T
A
= −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter +25°C 40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
SS
to V
DD
V V
DD
= +4.5 V, V
SS
= −4.5 V
On Resistance, R
ON
52 Ω typ V
S
= ±4.5 V, I
S
= 1 mA; see Figure 20
75 90 100 Ω max V
S
= ±4.5 V, I
S
= 1 mA; see Figure 20
On-Resistance Match
Between Channels, ΔR
ON
0.8 Ω typ V
S
= +3.5 V, I
S
= 1 mA
1.3 1.8 2 Ω max V
S
= +3.5 V, I
S
= 1 mA
On-Resistance Flatness, R
FLAT(ON)
9 Ω typ V
DD
= +5 V, V
SS
= −5 V, V
S
= ±3 V, I
S
= 1 mA
12 13 14 Ω max V
DD
= +5 V, V
SS
= −5 V, V
S
= ±3 V, I
S
= 1 mA
LEAKAGE CURRENTS V
DD
= +5.5 V, V
SS
= −5.5 V
Source Off Leakage, I
S(OFF)
±0.005 nA typ
V
D
= ±4.5 V, V
S
=
+
4.5 V; see Figure 21
±0.2 ±5 nA max
V
D
= ±4.5 V, V
S
=
+
4.5 V; see Figure 21
Drain Off Leakage, I
D(OFF)
±0.005 nA typ
V
D
= ±4.5 V, V
S
=
+
4.5 V; see Figure 22
±0.2 ±5 nA max
V
D
= ±4.5 V, V
S
=
+
4.5 V; see Figure 22
Channel On Leakage, I
D(ON)
, I
S(ON)
±0.005 nA typ V
D
= V
S
= ±4.5 V; see Figure 23
±0.2 ±5 nA max V
D
= V
S
= ±4.5 V; see Figure 23
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current, I
INL
or I
INH
0.005 μA typ V
IN
= V
INL
or V
INH
±1 μA max V
IN
= V
INL
or V
INH
Digital Input Capacitance, C
IN
2 pF typ
DYNAMIC CHARACTERISTICS
1
t
TRANSITION
60 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 24
90 110 130 ns max R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 24
t
ON
(
EN
)
70 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
95 120 135 ns max R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
t
OFF
(
EN
)
25 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
40 45 50 ns max R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
Break-Before-Make Time Delay, t
BBM
40 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S1
= V
S2
= 3 V; see Figure 25
10 ns min R
L
= 300 Ω, C
L
= 35 pF, V
S1
= V
S2
= 3 V; see Figure 25
Charge Injection 2 pC typ V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 27
4 pC max V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 27
Off Isolation −90 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion, THD + N 0.025 % typ R
L
= 600 Ω, 2 V p-p, f = 20 Hz to 20 kHz
Channel-to-Channel Crosstalk −90 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 30
−3 dB Bandwidth 580 MHz typ R
L
= 50 Ω, C
L
= 5 pF; see Figure 29
C
S(OFF)
4 pF typ f = 1 MHz
C
D(OFF)
7 pF typ f = 1 MHz
C
D(ON)
, C
S(ON)
12 pF typ f = 1 MHz
POWER REQUIREMENTS
2
V
DD
= +5.5 V, V
SS
= −5.5 V
I
DD
0.01 μA typ Digital inputs = 0 V or 5.5 V
1 μA max Digital inputs = 0 V or 5.5 V
I
SS
0.01 μA typ Digital inputs = 0 V or 5.5 V
1 μA max Digital inputs = 0 V or 5.5 V
1
Guaranteed by design; not subject to production test.
2
The device is fully specified at a ±5 V dual supply and at 5 V and 3.3 V single supplies. It is possible to operate the ADG633 with unbalanced supplies or at other voltage
supplies ( ±2 V to ±6 V, and 2 V to 12 V); however, the switch characteristics change. These changes include, but are not limited to: analog signal range, on resistance,
leakage, V
INL
, V
INH
, and switching times. The optimal power-up sequence for the device is: ground, V
DD
, V
SS
, and then the digital inputs, before applying the analog input
signal.
ADG633 Data Sheet
Rev. B | Page 4 of 16
SINGLE-SUPPLY OPERATION
V
DD
= 5 V, V
SS
= 0 V, GND = 0 V, T
A
= −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter +25°C 40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to V
DD
V V
DD
= 4.5 V, V
SS
= 0 V
On Resistance, R
ON
85 Ω typ V
S
= 0 V to 4.5 V, I
S
= 1 mA; see Figure 20
150 160 200 Ω max V
S
= 0 V to 4.5 V, I
S
= 1 mA; see Figure 20
On-Resistance Match
Between Channels, ΔR
ON
4.5 Ω typ V
S
= +3.5 V, I
S
= 1 mA
8 9 10 Ω max V
S
= +3.5 V, I
S
= 1 mA
On-Resistance Flatness, R
FLAT(ON)
13 14 16 Ω typ V
DD
= 5 V, V
SS
= 0 V, V
S
= 1.5 V to 4 V, I
S
= 1 mA
LEAKAGE CURRENTS V
DD
= 5.5 V
Source Off Leakage, I
S(OFF)
±0.005 nA typ V
S
= 1 V/4.5 V, V
D
= 4.5 V/1 V; see Figure 21
±5
nA max
V
S
= 1 V/4.5 V, V
D
= 4.5 V/1 V; see Figure 21
Drain Off Leakage, I
D(OFF)
nA typ
V
S
= 1 V/4.5 V, V
D
= 4.5 V/1 V; see Figure 22
±0.2 ±5 nA max V
S
= 1 V/4.5 V, V
D
= 4.5 V/1 V; see Figure 22
Channel On Leakage, I
D(ON)
, I
S(ON)
±0.005 nA typ V
S
= V
D
= 1 V or 4.5 V; see Figure 23
±0.2 ±5 nA max V
S
= V
D
= 1 V or 4.5 V; see Figure 23
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current, I
INL
or I
INH
0.005 μA typ V
IN
= V
INL
or V
INH
±1
μA max
V
IN
= V
INL
or V
INH
Digital Input Capacitance, C
IN
pF typ
DYNAMIC CHARACTERISTICS
1
t
TRANSITION
100 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 24
150 190 220 ns max R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 24
t
ON
(
EN
)
100 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
150 190 220 ns max R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
t
OFF
(
EN
)
25 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
35 45 50 ns max R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
Break-Before-Make Time Delay, t
BBM
90 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S1
= V
S2
= 3 V; see Figure 25
10 ns min R
L
= 300 Ω, C
L
= 35 pF, V
S1
= V
S2
= 3 V; see Figure 25
Charge Injection 0.5 pC typ V
S
= 2.5 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 27
pC max
V
S
= 2.5 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 27
Off Isolation
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 28
Channel-to-Channel Crosstalk
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 30
−3 dB Bandwidth 520 MHz typ R
L
= 50 Ω, C
L
= 5 pF; see Figure 29
C
S(OFF)
5 pF typ f = 1 MHz
C
D(OFF)
8 pF typ f = 1 MHz
C
D(ON)
, C
S(ON)
12 pF typ f = 1 MHz
POWER REQUIREMENTS
2
V
DD
= 5.5 V
I
DD
0.01 μA typ Digital inputs = 0 V or 5.5 V
1 μA max Digital inputs = 0 V or 5.5 V
1
Guaranteed by design; not subject to production test.
2
The device is fully specified at a ±5 V dual supply and at 5 V and 3.3 V single supplies. It is possible to operate the ADG633 with unbalanced supplies or at other voltage
supplies ( ±2 V to ±6 V, and 2 V to 12 V); however, the switch characteristics change. These changes include, but are not limited to: analog signal range, on resistance,
leakage, V
INL
, V
INH
, and switching times. The optimal power-up sequence for the device is: ground, V
DD
, V
SS
, and then the digital inputs, before applying the analog input
signal.
Data Sheet ADG633
Rev. B | Page 5 of 16
V
DD
= 2.7 V to 3.6 V, V
SS
= 0 V, G N D = 0 V, T
A
= −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to V
DD
V V
DD
= 2.7 V, V
SS
= 0 V
On Resistance, R
ON
185 Ω typ V
S
= 0 V to 2.7 V, I
S
= 0.1 mA; see Figure 20
300 350 400 Ω max V
S
= 0 V to 2.7 V, I
S
= 0.1 mA; see Figure 20
On-Resistance Match
Between Channels, ΔR
ON
2 Ω typ V
S
= +1.5 V, I
S
= 0.1 mA
4.5 6 7 Ω max V
S
= +1.5 V, I
S
= 0.1 mA
LEAKAGE CURRENTS V
DD
= 3.3 V
Source Off Leakage, I
S(OFF)
±0.005 nA typ V
S
= 1 V/3 V, V
D
= 3 V/1 V; see Figure 21
±0.2 ±5 nA max V
S
= 1 V/3 V, V
D
= 3 V/1 V; see Figure 21
Drain Off Leakage, I
D(OFF)
±0.005 nA typ V
S
= 1 V/3 V, V
D
= 3 V/1 V; see Figure 22
±0.2 ±5 nA max V
S
= 1 V/3 V, V
D
= 3 V/1 V; see Figure 22
Channel On Leakage, I
D(ON)
, I
S(ON)
±0.005 nA typ V
S
= V
D
= 1 V or 3 V; see Figure 23
±0.2 ±5 nA max V
S
= V
D
= 1 V or 3 V; see Figure 23
DIGITAL INPUTS
Input High Voltage, V
INH
2.0 V min
Input Low Voltage, V
INL
0.5 V max
Input Current, I
INL
or I
INH
0.005 μA typ V
IN
= V
INL
or V
INH
±1 μA max V
IN
= V
INL
or V
INH
Digital Input Capacitance, C
IN
2 pF typ
DYNAMIC CHARACTERISTICS
1
t
TRANSITION
170 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S
= 1.5 V; see Figure 24
300
370
400
ns max
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 1.5 V; see Figure 24
t
ON
(
EN
)
200
ns typ
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 1.5 V; see Figure 26
310
380
420
ns max
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 1.5 V; see Figure 26
t
OFF
(
EN
)
30 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S
= 1.5 V; see Figure 26
40 55 75 ns max R
L
= 300 Ω, C
L
= 35 pF, V
S
= 1.5 V; see Figure 26
Break-Before-Make Time Delay, t
BBM
180 ns typ R
L
= 300 Ω, C
L
= 35 pF, V
S1
= V
S2
= 1.5 V; see Figure 25
10 ns min R
L
= 300 Ω, C
L
= 35 pF, V
S1
= V
S2
= 1.5 V; see Figure 25
Charge Injection 1 pC typ V
S
= 1.5 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 27
2 pC max V
S
= 1.5 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 27
Off Isolation −90 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 28
Channel-to-Channel Crosstalk −90 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 30
−3 dB Bandwidth 500 MHz typ R
L
= 50 Ω, C
L
= 5 pF; see Figure 29
C
S(OFF)
5 pF typ f = 1 MHz
C
D(OFF)
8 pF typ f = 1 MHz
C
D(ON)
, C
S(ON)
12 pF typ f = 1 MHz
POWER REQUIREMENTS
2
V
DD
= 3.3 V
I
DD
0.01 μA typ Digital inputs = 0 V or 3.3 V
1 μA max Digital inputs = 0 V or 3.3 V
1
Guaranteed by design; not subject to production test.
2
The device is fully specified at a ±5 V dual supply and at 5 V and 3.3 V single supplies. It is possible to operate the ADG633 with unbalanced supplies or at other voltage
supplies ( ±2 V to ±6 V, and 2 V to 12 V); however, the switch characteristics change. These changes include, but are not limited to: analog signal range, on resistance,
leakage, V
INL
, V
INH
, and switching times. The optimal power-up sequence for the device is: ground, V
DD
, V
SS
, and then the digital inputs, before applying the analog input
signal.

ADG633YRUZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs 90dB 52 Ohm 580MHz CMOS Triple SPDT
Lifecycle:
New from this manufacturer.
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