AD8017
–9–REV. C
FREQUENCY kHz
+20
80
POWER dBm
20
40
60
0
0
50 100 150
TPC 23. Multitone Power Ratio: V
S
=
±
6 V, 13 dBm
Output Power into 25
FREQUENCY MHz
0.1 10001
CMRR dB
10 100
0
50
10
20
30
40
60
70
80
90
100
TPC 24. CMRR vs. Frequency; V
S
=
±
6 V or V
S
=
±
2.5 V
FREQUENCY kHz
0.01 1000.1
INPUT CURRENT NOISE nA/ Hz
110
0.4
0.3
0.1
0
0.2
12
10
6
0
8
4
2
INPUT VOLTAGE NOISE nA/ Hz
i
N
e
N
TPC 25. Noise vs. Frequency
SERIES RESISTANCE
120
20
CAP LOAD pF
80
60
40
100
0
24 8
0
6
TPC 26. R
S
and C
L
vs. 30% Overshoot
FREQUENCY MHz
0.1 10001
PSRR dB
10 100
0
50
10
20
30
40
60
70
80
PSRR
+PSRR
TPC 27. PSRR vs. Frequency; V
S
=
±
6 V or V
S
=
±
2.5 V
FREQUENCY MHz
0.001 10
TRANSIMPEDANCE k
0.1 1
1
180
0
120
60
PHASE Degrees
1000100
100
TRANSIMPEDANCE
PHASE
10
1000
0.01
TPC 28. Open-Loop Transimpedance and Phase vs.
Frequency
AD8017
–10–
REV. C
TIME ns
OUTPUT VOLTAGE ERROR mV/DIV (% /DIV)
G = +2
V
OUT
= 2V
STEP
R
L
- 100
V
S
= 6V
+2mV
(+0.1%)
2mV
(+0.1%)
0 102030405060708090
0
TPC 29. Settling Time; V
S
=
±
6.0 V
FREQUENCY MHz
0.1 10001
CROSSTALK dB
10 100
50
20
30
40
60
70
80
V
OUT
= 2V p-p
G = +2
R
L
= 100
90
100
TPC 30. Output Crosstalk vs. Frequency
FREQUENCY MHz
0.1 100
INPUT IMPEDANCE
110
100
0.1
10
1
OUTPUT IMPEDANCE
1000
1000
10000
100000
Z
IN
Z
OUT
1000000
TPC 31. Input and Output Impedance vs. Frequency
VOLTS
2
1
0
1
2
3
4
5
6
10 10 30 50 70 90 110 130 150
VOLTS
6
5
4
3
2
10 10 30 50 70 90 110 130 150
3
3
0
1
V
OUT
V
IN
V
OUT
V
IN
TIME ns
TPC 32. Overload Recovery; V
S
=
±
6 V, G = +2,
R
L
= 100
, V
IN
= 5 V p-p, T = 1
µ
s
AD8017
–11–REV. C
THEORY OF OPERATION
The AD8017 is a dual high speed CF amplifier that attains new
levels of bandwidth (BW), power, distortion and signal swing,
under heavy current loads. Its wide dynamic performance
(including noise) is the result of both a new complementary
high speed bipolar process and a new and unique architectural
design. The AD8017 basically uses a two gain stage comple-
mentary design approach versus the traditional “single stage”
complementary mirror structure sometimes referred to as the
Nelson amplifier. Though twin stages have been tried before,
they typically consumed high power since they were of a folded
cascode design much like the AD9617.
This design allows for the standing or quiescent current to add
to the high signal or slew current-induced stages. In the time
domain, the large signal output rise/fall time and slew rate is
typically controlled by the small signal BW of the amplifier and
the input signal step amplitude respectively, not the dc quies-
cent current of the gain stages (with the exception of input level
shift diodes Q1/Q2). Using two stages as opposed to one, also
allows for a higher overall gain bandwidth product (GBWP) for
the same power, thus providing lower signal distortion and the
ability to drive heavier external loads. In addition, the second
gain stage also isolates (divides down) A3’s input reflected load
drive and the nonlinearities created resulting in relatively lower
distortion and higher open-loop gain. See Figure 6.
Overall, when “high” external load drive and low ac distortion is
a requirement, a twin gain stage integrating amplifier like the
AD8017 will provide excellent results for low power over the
traditional single stage complementary devices. In addition,
being a CF amplifier, closed-loop BW variations versus external
gain variations (varying R
G
) will be much lower compared to a
VF op amp, where the BW varies inversely with gain. Another
key attribute of this amplifier is its ability to run on a single 5 V
supply due in part to its wide common-mode input and output
voltage range capability. For 5 V supply operation, the device
obviously consumes less than half the quiescent power (versus
12 V supply) with little degradation in its ac and dc performance
characteristics. See specification pages for comparisons.
DC GAIN CHARACTER
Gain stages A1/A1 and A2/A2 combined provide negative feed-
forward transresistance gain. See Figure 6. Stage A3 is a unity
gain buffer which provides external load isolation to A2. Each
stage uses a symmetrical complementary design. (A3 is also
complementary, though not explicitly shown). This is done to
reduce both second order signal distortion and overall quiescent
power as discussed above. In the quasi dc-to-low frequency
region, the closed loop gain relationship can be approximated as:
G = 1+R
F
/R
G
for Noninverting Operation
G = –R
F
/R
G
for Inverting Operation
These basic relationships above are common to all traditional
operational amplifiers.
A1
IPN
IQ1
Q3
IPP
V
P
+
Q1
Q2
Z1
Q4
INP
IPN
A1
V
N
IR + IFC
IR IFC
IQ1
IE
AD8017
V
I
C
P
1
V
I
C
P
1
A2
C
P
2
ICQ + IO
V
O
9
A3
A2
C
D
Z1
ICQ IO
R
N
R
F
Z2
R
L
C
L
V
O
Z1 = R1 || C1
Z1
C
D
Figure 6. Simplified Block Diagram

AD8017ARZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers Crnt Hi Outpt VTG Line Dvr
Lifecycle:
New from this manufacturer.
Delivery:
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