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AD8017ARZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD8017
–12–
REV. C
APPLICATIONS
Output Power Characteristics as Applied to ADSL Signals
The AD8017 was designed to provide both relatively high cur-
rent and voltage output capability. TPCs 12 and 15 quantify the
ac load current versus distortion of the device at loads of 100 Ω
and 25 Ω at 1 MHz. Using approximately –50 dBc as the worst
case distortion limit, the AD8017 exhibits acceptable linearity
to within approximately 1.4 V of either supply rail (12 V or ±6 V)
while simultaneously providing 200 mA of load current.
These levels are achieved at only 7 mA of quiescent current for
each amplifier.
ADSL applications require signal line powers of 13 dBm that
can randomly peak to an instantaneous power (or V × I product)
of 28.5 dBm. This equates to peak-to-rms voltage ratio of 5.3-
to-1. Using a 1:2 transformer in the ADSL circuit illustrated
below and 100 Ω as the line resistance, a peak voltage of 4.2 V
at a peak current of 168 mA will be required from the line driver
output (see Table I). See detailed application below. A higher
turns ratio transformer can be used to reduce the primary out-
put voltage swing of the amplifier (for devices that do not have
the voltage swing, but do have the current drive capability).
However, this requires more than an equivalent increase in
current due to the added I × R losses from the transformer for
the same receiver power. Generally this will result in added
distortion. Table I below shows the ADSL ac current and volt-
ages required for both a 1:1 and 1:2 transformer turns ratio.
V
IN
1k⍀
1k⍀
0.1␮F
0.1␮F
8
2
3
1
7
5
6
4.7V
4.7V
V
OUT
1:2
12V
1k⍀
0.1␮F
169⍀
169⍀
4
1k⍀
1␮F
1␮F
0.1␮F
10␮F
12.5⍀
12.5⍀
100⍀
AD8017
50⍀
EFFECTIVE
LOAD
Figure 7. Single 12 V Supply ADSL Remote Terminal
Transmitter
Table I. DSL Drive Amplifier Requirements for Various Combinations of Line Power, Line Impedance, and Turn Ratios
Line Insertion Line Turns Crest Reflected Per Amp Peak Per Amplifier Peak Current
Power Loss Load Ratio Factor Impedance R1 = R2 Voltage Voltage Output Output
13 dBm 1 dB 100 Ω 1:1 5.3 100 Ω 50 Ω 1.585 V rms 8.4 V peak 84 mA
13 dBm 1 dB 100 Ω 1:2 5.3 25 Ω 12.5 Ω 0.792 V rms 4.2 V peak 168 mA
Single 12 V Supply ADSL Remote Terminal (RT) Transmitter
For consumer use, it is desirable to create an ADSL modem
that can be a plug-in accessory for a PC. In such an application,
the circuit should dissipate a minimum of power, yet still meet
the ADSL specification.
The circuit in Figure 7 shows a single 12 V supply circuit that
uses the AD8017 as a remote terminal transmitter. This supply
voltage is readily available on the PCI connector of PCs. The
circuit configures each half of the AD8017 as an inverter with a
gain of about six. Both of the amplifier circuits are ac coupled at
both the inputs and the outputs. This makes the dc levels of the
circuit independent of the other dc levels of the signal chain.
The inputs will generally be driven by the output of an active
filter, which has a low output impedance. Thus there will be a
minimum of loading of the source caused by the 169 Ω input
impedance in the pass band. The output will require a 1:2 step-
up transformer to drive a 100 Ω line. The reflected impedance
back to the primary will be 25 Ω. With 25 Ω of series termina-
tion added (12.5 Ω in each output), the effective load that the
differential amplifier outputs will drive is 50 Ω.
The input and output ac coupling provides two high pass cir-
cuits. The inputs are formed by the 0.1 µF capacitor and the
169 Ω resistor, which provides a break frequency of about
9.4 kHz. The two 1 µF capacitors in the output along with the
50 Ω effective load provides a 6.4 kHz break frequency in the
output side. Both of these circuits want to reject the Plain Old
Telephone System (POTS) band (dc to 4 kHz) while passing
the ADSL upstream band, which starts at about 20 kHz.
The positive inputs must be biased at midsupply, which is nomi-
nally 6 V. This will maintain the maximum dynamic range of
the output in each direction, regardless of the tolerance of the
supply. The inverting configuration was chosen as this requires
a steady dc current from this supply, as opposed to the signal-
dependent current that would be required in a noninverting
configuration. Several options were studied for creating this supply.
A voltage regulator could be used, but there are several disad-
vantages. The first is that this will not track the middle of the
supplies as it will always have an output that is a fixed voltage
from ground. This also requires an additional active component
that will impact the cost of the total solution.
A two-resistor divider could also be used. There is a tradeoff
required here in the selection of the value of the resistors. As the
resistors become smaller, the amount of power that they will
dissipate will increase. For two 1 kΩ resistors, the power dissi-
pation in this circuit would be 72 mW. Thus, in order to keep
this power to a minimum, it is desirable to make the resistors as
large as possible.
AD8017
–13–REV. C
The practical maximum value that these resistors can have is
determined by the offset voltage that is created by the input bias
current that flows through them. The maximum input bias
current into the + inputs is 45 µA. This will create an offset
voltage of 45 mV per 1 kΩ of bias resistor. Fortunately, the ac
coupling of the stages provides only unity gain for this dc offset
voltage, which is another advantage of this configuration. Any
dc offset in the output will limit the amount of dynamic signal
swing that will be available between the rails.
The circuit shown uses two 4.7 V Zener diodes that provide a
voltage drop which serves to limit the power dissipation in the
bias circuit. This allows the use of smaller value resistors in the
bias circuit. Thus, for this circuit the current will be (12 V –
(2 × 4.7 V))/2 kΩ = 1.3 mA. Thus, this circuit will dissipate
only 15.6 mW, yet only induce a maximum of 40 mV of offset
at the output. This circuit will also track the midpoint of the
supplies over their specified tolerance range.
The distortion of the circuit was measured with a 50 Ω load.
The frequency used was 500 kHz, which is beyond the maxi-
mum required for the upstream signal. For ADSL over POTS,
a maximum frequency of 135 kHz is required. For ADSL over
ISDN, the maximum frequency is 276 kHz. The amplitude was
20 V p-p (10 V p-p for each amplifier), which is the maximum
crest signal that will be required. The second harmonic was better
than –80 dBc, while the third harmonic was –64 dBc. This
represents a worst case of the absolute maximum signal that will
be required for only a very small statistical basis and at a fre-
quency that is higher than the maximum required. For a statisti-
cal majority of the time, the signal will be at a lower amplitude
and frequency, where the distortion performance will be better.
When the circuit was run while providing the upstream drive signal
in an ADSL system, the supply current to the part was mea-
sured at 25 mA. Thus, the total power to the drive circuit was
300 mW. This power winds up in three places: the drive ampli-
fier, down the line and in the termination and interface circuitry.
The ADSL specification calls for 13 dBm or 20 mW into the line.
The line termination will consume an equal amount of power, as
it is the same resistance value. About a 1 dB loss can be expected
in the losses in the interface circuitry, which translates into about
10 mW of power. Thus, the total power dissipated in the AD8017
when used as a driver in this application is about 250 mW.
A1
A1
R
L
V
O1
V
O2
VCC
VEE
Figure 8. Differential Driver Simplified Circuit Schematic
It is important to consider the total power dissipation of the
AD8017 in order to properly size the heat sinking area for your
application. The dc power dissipation for V
IN
= 0 is simply,
I
Q
. (V
CC
+ V
EE
), or 2 × I
Q
× V
S
. For the AD8017, this number is
0.17 W. In this purely differential circuit we can use symmetry
to simplify the computation for a dc input signal,
PIVVV
V
R
DQS SO
O
L
=× × +×
()
×24–
This formula is slightly pessimistic due to the fact that some of
the quiescent supply current commutates during sourcing or
sinking current into the load. For a sine wave source, integration
over a half cycle yields:
PIV
VV
R
V
R
DQS
OS
L
O
L
=× × +× −
22
4
2
π
(Refer to Figure 41)
The situation is more complicated with a complex modulated
signal. In the case of a DMT signal, taking the equivalent sine wave
power overestimates the power dissipation by > 15%. For example:
P
OUT
= 16 dBm = 40 mW
V
OUT
@ 50 Ω = 1.41 V rms or V
O
= 1.0 V
at each amplifier output, which yields a P
D
of 0.436 W. By
actual measurement, P
D
for a DMT signal of 16 dBm requires
0.38 W of power to be dissipated by the AD8017.
OUTPUT VOLTAGE (V
O
) – V
PK
POWER DISSIPATION (P
D
) – W
0.8
0
0.2
41203
0.3
0.4
0.5
0.6
0.7
0.1
56
Figure 9. Power Dissipation (P
D
) vs. Output Voltage (V
O
),
R
L
= 50
Ω
Thermal Considerations
The AD8017 in a “Thermal Coastline” SO-8 package relies on
the device pins to assist in removing heat from the die at a faster
rate than that of conventional packages. The effect is to provide
a lower θ
JC
for the device. To make the most effective use of
this, special details should be worked into the copper traces of
the printed circuit board.
There will be a tradeoff, however, between designing a board
that will maximally remove heat, and one that will provide the
desired ac performance. This is the result of the additional para-
sitic capacitance on some of the pins that would be caused by
the addition of extra heat sinking copper traces.
AD8017
–14–
REV. C
The first technique for maximum heat sinking is to use a heavy
layer of copper. 2 oz. copper will provide better heat sinking
than 1 oz. copper. Additional internal circuit layers can also be
used to more effectively remove heat, and to provide better
power and ground distribution.
There are no “ground” pins per se on the AD8017 (when run
on a dual supply), but the power supplies (Pins 4 and 8) are at
ac ground. Thus, these pins can be safely tied to a maximum
area of copper foil without affecting the ac performance of the
part. On the surface side of the board, the copper area that
connects to Pins 4 and 8 should be enlarged and spread out to
the maximum extent possible. As a practical matter, there will
be diminishing returns from adding copper more than a few
centimeters from the pins.
When the power supplies are run on the board on internal
power planes, then these should also be made as large as practi-
cal, and multiple vias (~0.012 in. or 0.3 mm) should be provided
from the component layer near the power supply pins of the
AD8017 to the inner layers. These vias should not have any of
the traditional “thermal relief” spokes to the planes, because the
function of these is to impede heat flow for ease of soldering.
This is counter to the effect desired for heat sinking.
On the side of the board opposite the component, additional
heat sinking can be provided by adding copper area near the vias
to further lower the thermal resistance. Additional vias can be
provided throughout to better conduct heat from the inner layers
to the outer layers.
The remainder of the device pins are active signal pins and must
be treated a bit more carefully. Pins 2 and 6 are the summing
junctions of the op amps and will be the most adversely affected by
stray capacitance. For this reason, the copper area of these pins
should be minimized. In addition, the copper nearby on the
component layer should be kept more than 3 mm–5 mm away
from these pins, where possible. The inner and opposite side
circuit layers directly below the summing junctions should also
be void of copper.
The positive inputs and outputs can withstand somewhat more
capacitance than the summing junctions without adversely
affecting ac performance. However, these pins should be treated
carefully, and the amount of heat sinking and excess capacitance
should be analyzed and adjusted depending on the application.
If maximum ac performance is desired and the power dissipa-
tion is not extreme, then the copper area connected to these pins
should be minimized. If the ac performance is not very critical
and maximum power must be dissipated, then the copper area
connected to these pins can be increased. As in many other
areas of analog design, the designer must use some judgment
based on the consideration of the above, in order to produce a
satisfactory design.
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8017 requires
careful attention to board layout and component selection.
Table II shows recommended component values for the AD8017
and Figures 10–12 show recommended layouts for the 8-lead
SOIC package for a positive gain. Proper RF design techniques
and low parasitic component selections are mandatory.
Table II. Typical Bandwidth vs. Gain Setting Resistors
(V
S
= 6 V, R
L
= 100 ⍀)
Small Signal
Gain R
F
(⍀)R
G
(⍀)R
T
(⍀) –3 dB BW (MHz)
–1 619 619 54.5 110
+1 619 49.9 320
+2 619 619 49.9 160
+10 619 68.8 49.9 40
R
T
chosen for 50 Ω characteristic input impedance.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Fig-
ures 4 and 5). One end should be connected to the ground
plane and the other within 1/8 in. of each power pin. An addi-
tional (4.7 µF–10 µF) tantalum electrolytic capacitor should be
connected in parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to
a minimum. Capacitance greater than 1.5 pF at the inverting
input will significantly affect high speed performance when
operating at low noninverting gain.
Figure 10. Universal SOIC Noninverter Top Silkscreen
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD8017ARZ-REEL

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High Speed Operational Amplifiers Crnt Hi Outpt VTG Line Dvr
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