14
FN6313.0
June 22, 2006
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1 – Alarm set with single interrupt (IM = ”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm registers as follows:
B. Also the ALME bit must be set as follows:
xx indicate other control bits
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ
output low.
Example 2 – Pulsed interrupt once per minute (IM=”1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm registers as follows:
B. Set the Interrupt register as follows:
xx indicate other control bits
Once the registers are set, the following waveform will be
seen at IRQ-:
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
User Registers
Addresses [12h to 19h]
These registers are 8 bytes of battery-backed user memory
storage.
I
2
C Serial Interface
The ISL1218 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is the master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL1218
operates as a slave device in all applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 12). On power up of the ISL1218, the SDA pin is in
the input mode.
All I
2
C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL1218 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 12). A START condition is ignored during the
power-up sequence.
All I
2
C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 12). A STOP condition at the end
of a read operation or at the end of a write operation to
memory only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 13).
ALARM
REGISTER
BIT
DESCRIPTION76543210HEX
SCA 00000000 00hSeconds disabled
MNA 10110000B0hMinutes set to 30,
enabled
HRA 10010001 91hHours set to 11,
enabled
DTA 10000001 81hDate set to 1,
enabled
MOA 10000001 81hMonth set to 1,
enabled
DWA 00000000 00hDay of week
disabled
CONTROL
REGISTER
BIT
DESCRIPTION76543210HEX
INT 01xx0000 x0hEnable Alarm
ALARM
REGISTER
BIT
DESCRIPTION76543210HEX
SCA 10110000B0hSeconds set to 30,
enabled
MNA 0000000000hMinutes disabled
HRA 0000000000hHours disabled
DTA 0000000000hDate disabled
MOA 0000000000hMonth disabled
DWA 0000000000hDay of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION76543210HEX
INT 11xx0000x0hEnable Alarm and Int
Mode
60 SEC
RTC AND ALARM REGISTERS ARE BOTH “30” SEC
ISL1218
