ISL1218IUZ Datasheet ISL1218IBZ, ISL1218IUZ, ISL1218IBZ-T | P16-P18

FN6313.0

June 22, 2006

Device Addressing

Following a start condition, the master must output a Slave

Address Byte. The 7 MSBs are the device identifier. These

bits are “1101111”. Slave bits “1101” access the register.

Slave bits “111” specify the device select bits.

The last bit of the Slave Address Byte defines a read or write

operation to be performed. When this R/W

bit is a “1”, then a

read operation is selected. A “0” selects a write operation

(Refer to Figure 15).

After loading the entire Slave Address Byte from the SDA

bus, the ISL1218 compares the device identifier and device

select bits with “1101111”. Upon a correct compare, the

device outputs an acknowledge on the SDA line.

Following the Slave Byte is a one byte word address. The

word address is either supplied by the master device or

obtained from an internal counter. On power up the internal

address counter is set to address 0h, so a current address

read of the CCR array starts at address 0h. When required,

as part of a random read, the master must supply the 1 Word

Address Bytes as shown in Figure 16.

In a random read operation, the slave byte in the “dummy

write” portion must match the slave byte in the “read”

section. For a random read of the Clock/Control Registers,

the slave byte must be “1101111x” in both places.

Write Operation

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte,

and a STOP condition. After each of the three bytes, the

ISL1218 responds with an ACK. At this time, the I

interface enters a standby state.

Read Operation

A Read operation consists of a three byte instruction

followed by one or more Data Bytes (See Figure 16). The

master initiates the operation issuing the following

sequence: a START, the Identification byte with the R/W

bit

set to “0”, an Address Byte, a second START, and a second

Identification byte with the R/W

bit set to “1”. After each of

the three bytes, the ISL1218 responds with an ACK. Then

the ISL1218 transmits Data Bytes as long as the master

responds with an ACK during the SCL cycle following the

eighth bit of each byte. The master terminates the read

operation (issuing a STOP condition) following the last bit of

the last Data Byte (See Figure 16).

The Data Bytes are from the memory location indicated by

an internal pointer. This pointer initial value is determined by

the Address Byte in the Read operation instruction, and

increments by one during transmission of each Data Byte.

After reaching the memory location 19h the pointer “rolls

over” to 00h, and the device continues to output data for

each ACK received.

FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA

BYTES

SLAVE

ADDRESS BYTE

D7 D6 D5 D2D4 D3 D1 D0

A0A7 A2A4 A3 A1

DATA BYTE

A6 A5

R/W

WORD ADDRESS

FIGURE 16. READ SEQUENCE

SIGNALS

FROM THE

MASTER

SIGNALS FROM

THE SLAVE

SIGNAL AT

SDA

IDENTIFICATION

BYTE WITH

R/W

ADDRESS

BYTE

IDENTIFICATION

BYTE WITH

R/W

= 1

LAST READ

DATA BYTE

FIRST READ

DATA BYTE

101 1111

101

ISL1218

FN6313.0

June 22, 2006

Application Section

Oscillator Crystal Requirements

The ISL1218 uses a standard 32.768kHz crystal. Either

through hole or surface mount crystals can be used. Table 6

lists some recommended surface mount crystals and the

parameters of each. This list is not exhaustive and other

surface mount devices can be used with the ISL1218 if their

specifications are very similar to the devices listed. The

crystal should have a required parallel load capacitance of

12.5pF and an equivalent series resistance of less than 50k.

The crystal’s temperature range specification should match

the application. Many crystals are rated for -10°C to +60°C

(especially through hole and tuning fork types), so an

appropriate crystal should be selected if extended

temperature range is required.

Crystal Oscillator Frequency Adjustment

The ISL1218 device contains circuitry for adjusting the

frequency of the crystal oscillator. This circuitry can be used

to trim oscillator initial accuracy as well as adjust the

frequency to compensate for temperature changes.

The Analog Trimming Register (ATR) is used to adjust the

load capacitance seen by the crystal. There are six bits of

ATR control, with linear capacitance increments available for

adjustment. Since the ATR adjustment is essentially “pulling”

the frequency of the oscillator, the resulting frequency

changes will not be linear with incremental capacitance

changes. The equations which govern pulling show that

lower capacitor values of ATR adjustment will provide larger

increments. Also, the higher values of ATR adjustment will

produce smaller incremental frequency changes. These

values typically vary from 6-10 ppm/bit at the low end to

<1ppm/bit at the highest capacitance settings. The range

afforded by the ATR adjustment with a typical surface mount

crystal is typically -34 to +80ppm around the ATR=0 default

setting because of this property. The user should note this

when using the ATR for calibration. The temperature drift of

the capacitance used in the ATR control is extremely low, so

this feature can be used for temperature compensation with

good accuracy.

In addition to the analog compensation afforded by the

adjustable load capacitance, a digital compensation feature

is available for the ISL1218. There are 3 bits known as the

Digital Trimming Register (DTR). The range provided is

±60ppm in increments of 20ppm. DTR operates by adding or

skipping pulses in the clock counter. It is very useful for

coarse adjustments of frequency drift over temperature or

extending the adjustment range available with the ATR

Initial accuracy is best adjusted by enabling the frequency

output (using the INT register, address 08h), and monitoring

the ~IRQ/F

OUT

pin with a calibrated frequency counter.

The frequency used is unimportant, although 1Hz is the

easiest to monitor. The gating time should be set long

enough to ensure accuracy to at least 1ppm. The ATR

should be set to the center position, or 100000Bh, to begin

with. Once the initial measurement is made, then the ATR

increasing the ATR register for increased capacitance will

lower the frequency, and vice-versa. If the initial

measurement shows the frequency is far off, it will be

necessary to use the DTR register to do a coarse

adjustment. Note that most all crystals will have tight enough

initial accuracy at room temperature so that a small ATR

Temperature Compensation

The ATR and DTR controls can be combined to provide

crystal drift temperature compensation. The typical

32.768kHz crystal has a drift characteristic that is similar to

that shown in Figure 17. There is a turnover temperature

) where the drift is very near zero. The shape is parabolic

as it varies with the square of the difference between the

actual temperature and the turnover temperature.

If full industrial temperature compensation is desired in an

ISL1218 circuit, then both the DTR and ATR registers will

need to be utilized (total correction range = -94 to +140ppm).

TABLE 6. SUGGESTED SURFACE MOUNT CRYSTALS

MANUFACTURER PART NUMBER

Citizen CM200S

Epson MC-405, MC-406

Raltron RSM-200S

SaRonix 32S12

Ecliptek ECPSM29T-32.768K

ECS ECX-306

Fox FSM-327

TEMPERATURE (°C)

-160.0

-140.0

-120.0

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

-40-30-20-100 1020304050607080

PPM

FIGURE 17. RTC CRYSTAL TEMPERATURE DRIFT

ISL1218

FN6313.0

June 22, 2006

A system to implement temperature compensation would

consist of the ISL1218, a temperature sensor, and a

microcontroller. These devices may already be in the system

so the function will just be a matter of implementing software

and performing some calculations. Fairly accurate

temperature compensation can be implemented just by

using the crystal manufacturer’s specifications for the

turnover temperature T

and the drift coefficient (β). The

formula for calculating the oscillator adjustment necessary

is:

Adjustment (ppm) = (T – T

)

* β

Once the temperature curve for a crystal is established, then

the designer should decide at what discrete temperatures

the compensation will change. Since drift is higher at

extreme temperatures, the compensation may not be

needed until the temperature is greater than 20°C from T

A sample curve of the ATR setting vs. Frequency Adjustment

for the ISL1218 and a typical RTC crystal is given in

Figure 18. This curve may vary with different crystals, so it is

good practice to evaluate a given crystal in an ISL1218

circuit before establishing the adjustment values.

This curve is then used to figure what ATR and DTR settings

are used for compensation. The results would be placed in a

lookup table for the microcontroller to access.

Layout Considerations

The crystal input at X1 has a very high impedance, and

oscillator circuits operating at low frequencies such as

32.768kHz are known to pick up noise very easily if layout

precautions are not followed. Most instances of erratic

clocking or large accuracy errors can be traced to the

susceptibility of the oscillator circuit to interference from

adjacent high speed clock or data lines. Careful layout of the

RTC circuit will avoid noise pickup and insure accurate

clocking.

Figure 19 shows a suggested layout for the ISL1218 device

using a surface mount crystal. Two main precautions should

be followed:

Do not run the serial bus lines or any high speed logic lines

in the vicinity of the crystal. These logic level lines can

induce noise in the oscillator circuit to cause misclocking.

Add a ground trace around the crystal with one end

terminated at the chip ground. This will provide termination

for emitted noise in the vicinity of the RTC device.

In addition, it is a good idea to avoid a ground plane under

the X1 and X2 pins and the crystal, as this will affect the load

capacitance and therefore the oscillator accuracy of the

circuit. If the ~IRQ/F

OUT

pin is used as a clock, it should be

routed away from the RTC device as well. The traces for the

BAT

and V

pins can be treated as a ground, and should

be routed around the crystal.

Super Capacitor Backup

The ISL1218 device provides a V

BAT

pin which is used for a

battery backup input. A Super Capacitor can be used as an

alternative to a battery in cases where shorter backup times

are required. Since the battery backup supply current

required by the ISL1218 is extremely low, it is possible to get

months of backup operation using a Super Capacitor.

Typical capacitor values are a few µF to 1 Farad or more

depending on the application.

If backup is only needed for a few minutes, then a small

inexpensive electrolytic capacitor can be used. For extended

periods, a low leakage, high capacity Super Capacitor is the

best choice. These devices are available from such vendors

as Panasonic and Murata. The main specifications include

working voltage and leakage current. If the application is for

charging the capacitor from a +5V ±5% supply with a signal

diode, then the voltage on the capacitor can vary from ~4.5V

to slightly over 5.0V. A capacitor with a rated WV of 5.0V

may have a reduced lifetime if the supply voltage is slightly

high. The leakage current should be as small as possible.

For example, a Super Capacitor should be specified with

leakage of well below 1µA. A standard electrolytic capacitor

with DC leakage current in the microamps will have a

severely shortened backup time.

Below are some examples with equations to assist with

calculating backup times and required capacitance for the

ISL1218 device. The backup supply current plays a major

part in these equations, and a typical value was chosen for

-40.0

-30.0

-20.0

-10.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

0 5 10 15 20 25 30 35 40 45 50 55 60

ATR SETTING

PPM ADJUSTMENT

FIGURE 18. ATR SETTING vs OSCILLATOR FREQUENCY

ADJUSTMENT

FIGURE 19. SUGGESTED LAYOUT FOR ISL1218 AND

CRYSTAL

ISL1218

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

ISL1218IUZ

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Real Time Clock REAL TIME CLKRTC IN

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