19
FN6313.0
June 22, 2006
example purposes. For a robust design, a margin of 30%
should be included to cover supply current and capacitance
tolerances over the results of the calculations. Even more
margin should be included if periods of very warm
temperature operation are expected.
Example 1. Calculating Backup Time Given
Voltages and Capacitor Value
In Figure 20, use C
BAT
= 0.47F and V
CC
= 5.0V. With V
CC
=
5.0V, the voltage at V
BAT
will approach 4.7V as the diode
turns off completely. The ISL1218 is specified to operate
down to V
BAT
= 1.8V. The capacitance charge/discharge
equation is used to estimate the total backup time:
Rearranging gives
C
BAT
is the backup capacitance and dV is the change in
voltage from fully charged to loss of operation. Note that
I
TOT
is the total of the supply current of the ISL1218 (I
BAT
)
plus the leakage current of the capacitor and the diode, I
LKG
.
In these calculations, I
LKG
is assumed to be extremely small
and will be ignored. If an application requires extended
operation at temperatures over 50°C, these leakages will
increase and hence reduce backup time.
Note that I
BAT
changes with V
BAT
almost linearly (see
Typical Performance Curves). This allows us to make an
approximation of I
BAT
, using a value midway between the
two endpoints. The typical linear equation for I
BAT
vs V
BAT
is:
Using this equation to solve for the average current given 2
voltage points gives:
Combining with Equation 2 gives the equation for backup
time:
where:
C
BAT
= 0.47F
V
BAT2
= 4.7V
V
BAT1
= 1.8V
I
LKG
= 0 (assumed minimal)
Solving equation 4 for this example, I
BATAVG
= 4.387E-7 A
T
BACKUP
= 0.47 * (2.9) / 4.38E-7 = 3.107E6 sec
Since there are 86,400 seconds in a day, this corresponds to
35.96 days. If the 30% tolerance is included for capacitor
and supply current tolerances, then worst case backup time
would be:
C
BAT
= 0.70 * 35.96 = 25.2 days
Example 2. Calculating a Capacitor Value for a
Given Backup Time
Referring to Figure 20 again, the capacitor value needs to be
calculated to give 2 months (60 days) of backup time, given
V
CC
= 5.0V. As in Example 1, the V
BAT
voltage will vary from
4.7V down to 1.8V. We will need to rearrange Equation 2 to
solve for capacitance:
Using the terms described above, this equation becomes:
where:
T
BACKUP
= 60 days * 86,400 sec/day = 5.18 E6 sec
I
BATAVG
= 4.387 E-7 A (same as Example 1)
I
LKG
= 0 (assumed)
V
BAT2
= 4.7V
V
BAT1
= 1.8V
Solving gives:
C
BAT
= 5.18 E6 * (4.387 E-7)/(2.9) = 0.784F
If the 30% tolerance is included for tolerances, then worst
case cap value would be:
C
BAT
= 1.3 *.784 = 1.02F
FIGURE 20. SUPERCAPACITOR CHARGING CIRCUIT
2.7V to 5.5V
V
CC
V
BAT
GND
1N4148
C
BAT
I = C
BAT
* dV/dT
(EQ. 1)
dT = C
BAT
* dV/I
TOT
to solve for backup time.
(EQ. 2)
I
BAT
= 1.031E-7*(V
BAT
) + 1.036E-7 Amps
(EQ. 3)
I
BATAVG
= 5.155E-8*(V
BAT2
+ V
BAT1
) + 1.036E-7 Amps
(EQ. 4)
T
BACKUP
= C
BAT
* (V
BAT2
- V
BAT1
) / (I
BATAVG
+ I
LKG
)
(EQ. 5)
seconds
C
BAT
= dT*I/dV
(EQ. 6)
C
BAT
= T
BACKUP
* (I
BATAVG
+ I
LKG
)/(V
BAT2
– V
BAT1
)
(EQ. 7)
ISL1218
20
FN6313.0
June 22, 2006
ISL1218
Mini Small Outline Plastic Packages (MSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums and to be determined at Datum plane
.
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
L
0.25
(0.010)
L1
R1
R
4X θ
4X θ
GAUGE
PLANE
SEATING
PLANE
EE1
N
12
TOP VIEW
INDEX
AREA
-C-
-B-
0.20 (0.008) A
B
C
SEATING
PLANE
0.20 (0.008) C
0.10 (0.004) C
-A-
-H-
SIDE VIEW
b
e
D
A
A1
A2
-B-
END VIEW
0.20 (0.008) C
D
E
1
C
L
C
a
- H -
-A -
- B -
- H -
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.037 0.043 0.94 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.030 0.037 0.75 0.95 -
b 0.010 0.014 0.25 0.36 9
c 0.004 0.008 0.09 0.20 -
D 0.116 0.120 2.95 3.05 3
E1 0.116 0.120 2.95 3.05 4
e 0.026 BSC 0.65 BSC -
E 0.187 0.199 4.75 5.05 -
L 0.016 0.028 0.40 0.70 6
L1 0.037 REF 0.95 REF -
N8 87
R 0.003 - 0.07 - -
R1 0.003 - 0.07 - -
05
o
15
o
5
o
15
o
-
α
0
o
6
o
0
o
6
o
-
Rev. 2 01/03
21
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6313.0
June 22, 2006
ISL1218
Small Outline Plastic Packages (SOIC)
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H
0.25(0.010) BM M
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
α
-
Rev. 1 6/05

ISL1218IUZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock REAL TIME CLKRTC IN
Lifecycle:
New from this manufacturer.
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