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SL28748ELI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 10 of 19
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD# is sampled LOW by two consecutive rising edges
of CPU clocks, all single-ended outputs will be held LOW on
their next HIGH-to-LOW transition and differential clocks must
held LOW. When PD# mode is desired as the initial power on
state, PD# must be asserted LOW in less than 10 s after
asserting CKPWRGD.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from are driven high in less than 300 s of
PD# deassertion to a voltage greater than 200 mV. After the
clock chip’s internal PLL is powered up and locked, all outputs
are enabled within a few clock cycles of each clock. Figure 2
is an example showing the relationship of clocks coming up.
Table 6. Output Driver Status
All Single-ended Clocks All Differential Clocks
w/o Strap w/ Strap Clock Clock#
PD# = 0 (Power down)
Low Hi-z Low Low
Figure 2. Power Down Deassertion Timing Waveform
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 11 of 19
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
Figure 3. CKPWRGD Timing Diagram
CPU_STP#
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
Tdrive_CPU_STP#,10 ns>200 mV
CPUC Internal
Figure 5. CPU_STP# Deassertion Waveform
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 12 of 19
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
V
DD_3.3V
Main Supply Voltage Functional – 4.6 V
V
DD_IO
IO Supply Voltage Functional 4.6 V
V
IN
Input Voltage Relative to V
SS
–0.5 4.6 V
DC
T
S
Temperature, Storage Non-functional –65 150 °C
T
A
Temperature, Operating
Ambient (Commercial)
Functional 0 85 °C
T
A
Temperature, Operating
Ambient (Industrial)
Functional -40 85 °C
T
J
Temperature, Junction Functional – 150 °C
Ø
JC
Dissipation, Junction to Case Functional – 20 °C/
W
Ø
JA
Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/
W
ESD
HBM
ESD Protection (Human Body
Model)
JEDEC (JESD 51) 2000 – V
UL-94 Flammability Rating JEDEC (JESD 22 - A114) V–0
MSL Moisture Sensitivity Level UL (Class) 1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VDD core 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
V
IH
3.3V Input High Voltage (SE) 2.0 V
DD
+ 0.3 V
V
IL
3.3V Input Low Voltage (SE) V
SS
– 0.3 0.8 V
V
IHI2C
Input High Voltage SDATA, SCLK 2.2 – V
V
ILI2C
Input Low Voltage SDATA, SCLK – 1.0 V
V
IH_FS
FS Input High Voltage 0.7 VDD+0.3 V
V
IL_FS
FS Input Low Voltage V
SS
– 0.3 0.35 V
I
IH
Input High Leakage Current Except internal pull-down resistors, 0 < V
IN
< V
DD
–5A
I
IL
Input Low Leakage Current Except internal pull-up resistors, 0 < V
IN
< V
DD
–5 – A
V
OH
3.3V Output High Voltage (SE) I
OH
= –1 mA 2.4 – V
V
OL
3.3V Output Low Voltage (SE) I
OL
= 1 mA – 0.4 V
V
DD IO
Low Voltage IO Supply Voltage 1 3.465 V
I
OZ
High-impedance Output
Current
–10 10 A
C
IN
Input Pin Capacitance 1.5 5 pF
C
OUT
Output Pin Capacitance 6pF
L
IN
Pin Inductance – 7 nH
V
XIH
Xin High Voltage 0.7V
DD
V
DD
V
V
XIL
Xin Low Voltage 0 0.3V
DD
V
IDD_
PD
Power Down Current – 1 mA
I
DD_3.3V
Dynamic Supply Current All outputs enabled. SE clocks with 8” traces.
Differential clocks with 7” traces. Loading per
CK505 spec.
–65mA
I
DD_VDD_IO
Dynamic Supply Current All outputs enabled. SE clocks with 8” traces.
Differential clocks with 7” traces. Loading per
CK505 spec.
–25mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

SL28748ELI

Mfr. #:
Buy SL28748ELI
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Calpella, IronLake, Jasper Forest, Ibex Peak.
Lifecycle:
New from this manufacturer.
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