DOC#: SP-AP-0017 (Rev. AA) Page 19 of 19
Document History Page
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Document Title: SL28748 PC EProClock
®
Generator for Intel Calpella Chipset
DOC#: SP-AP-0017 (Rev. AA)
REV. ECR#
Issue
Date
Orig. of
Change Description of Change
1.0 10/09/08 JMA Initial Release
1.1 10/23/08 JMA 1. Changed operating temperature to 0-85C
2. Re-aligned ordering part number description
1.2 1/27/09 JMA 1. Updated Rev. ID
2. Updated definition of Byte 6 bit 5 and 3
3. Updated Byte 13 and single-ended slew rate table
4. Updated Byte 14
5. Updated Feature description
6. Added less than symbol in power consumption value
7. Updated ordering part number
8. Changed package information
9. Changed Wireless Friendly Mode to 111
1.3 3/16/09 JMA 1. Added PC EProClock
®
Programmed Technology in Feature section
2. Updated Block Diagram
3. Updated 27MHz slew rate measurement window
4. Updated power consumption
1.4 3/25/09 JMA 1. Updated Package information removed punch version with saw version
2. Updated Period at 100MHz for CPU clocks
3. Updated Revision ID
4. Added Power down Spec
5. Added PC EProClock
®
Technology description
6. Added CPU Skew
1.5 6/03/09 JMA 1. Updated Revision ID
2. Removed 3-bit differential slew rate
3. Removed 0.1s from CPU duty cycle spec
4. Changed SATA PLL2 to PLL4
5. Updated IDD measurement condition
1.6 10/16/09 JMA 1. Removed the word “Preliminary”
2. Added Note in package diagram
3. Updated text content
4. Added information on trace length in Figure 8
5. Removed CPU Driven Figures
6. Edited CK_PWRGD to CKPWRGD
AA 1456 05/18/10 JMA 1. Updated MIL-STD to Jedec Standard
2. Updated VDD_IO spec to 4.6V maximum value
3. Combined Commercial and Industrial
4. Changed Revision to be ISO compliant
5. Removed refernce to Application Note#25.
6. Added feature for clock input
7. Removed skew data on REF clock
