DS2726G+ Datasheet DS2726G+ | P10-P12

DS2726

Li+ Protection Conditions

Overvoltage, OV. If any cell voltage (V

CELL

) exceeds

the overvoltage threshold, V

, for a period longer than

overvoltage delay, t

OVD

, the DS2726 shuts off the

external charge FET. When V

CELL

falls below the

charge-enable threshold V

, the DS2726 turns the

charge FET on. The discharge FET remains enabled

during the overvoltage event. Care should be taken

while discharging during an OV condition because the

current drawn by the load is going through the body

diode of the CC FET.

Undervoltage, UV. If V

CELL

drops below the undervolt-

age threshold, V

, for a period longer than undervolt-

age delay, t

UVD

, the DS2726 shuts off the charge and

discharge FETs and enters Sleep Mode. The device

remains in Sleep Mode until a charger is detected, at

which point the DS2726 wakes up and enables the CC

FET. The DC FET remains disabled until every cell is

above the V

UV_REL

threshold. Care should be taken

while charging during a UV event because the charge

current is flowing through the body diode of the DC FET.

Discharge Overcurrent, DOC. If V

SNS

is less than

RDOC

for a period longer than t

DOCD

, the DS2726

shuts off the external discharge FET. The discharge

current path is not reestablished until V

PKP

rises above

VIN

- V

. The DS2726 provides a test current of value

TST

from the PKP pin to the V

pin to detect the

removal of the offending low-impedance load. I

TST

not disabled if an undervoltage condition is reached.

Short Circuit, SC. If V

SNS

is less than V

RSC

for a peri-

od longer than short-circuit delay t

SCD

, the DS2726

shuts off the external discharge FET. The discharge

current path is not reestablished until V

PKP

rises above

VIN

- V

. The DS2726 provides a test current of value

TST

from the PKP pin to the V

pin to detect the

removal of the short. I

TST

is disabled if an undervoltage

condition is reached.

Summary. All the protection conditions described are

logic ORed to affect the CC and DC outputs:

DC = (Undervoltage) or (Discharge Overcurrent) or

(Short Circuit)

CC = (Overvoltage) or (Undervoltage and Charger

Detect)

5-Cell to 10-Cell Li+ Protector with

Cell Balancing

10 ______________________________________________________________________________________

CELL

SNS

RSC

RDOC

OVD

UVD

OCD

SCD

CHARGE

DISCHARGE

POWER

MODE

ACTIVE

SLEEP

OHCC

OLCC

OLDC

OHDC

UV_REL

Figure 3. Li+ Protection Circuitry Example Waveforms

Configuration for Number of Cells

The DS2726 protects 5 to 10 Li+-based cells connect-

ed in series. The number of cells is configured using

the SEL0 and SEL1 pins according to Table 2.

Pin V10 should always be connected to the positive ter-

minal of the battery stack regardless of the number of

cells in the stack. Cell connections that are not in use

for battery stacks with fewer than 10 cells should be

shorted to the cell connection below it. For example, a

stack with 9 cells would have V9 shorted to V8 and V8

connected to the positive terminal of the 8th cell; a

stack with 8 cells would have V9 shorted to V8 shorted

to V7 and V7 connected to the positive terminal of the

7th cell, and so on (see Figure 4).

Cell Connection Order

Care must be taken when connecting cells to the

DS2726 to avoid damaging the device. GND should be

connected first, then V

. Next, V0 should be connect-

ed, then V1 and so on until V10 is connected last.

DS2726

5-Cell to 10-Cell Li+ Protector with

Cell Balancing

______________________________________________________________________________________ 11

9 CELLS

V10

V09

V08

V07

V06

V05

V04

V03

V02

V01

V00

8 CELLS

V10

V09

V08

V07

V06

V05

V04

V03

V02

V01

V00

7 CELLS

V10

V09

V08

V07

V06

V05

V04

V03

V02

V01

V00

6 CELLS

V10

V09

V08

V07

V06

V05

V04

V03

V02

V01

V00

5 CELLS

V10

V09

V08

V07

V06

V05

V04

V03

V02

V01

V00

Figure 4. Cell Bypassing Connection

Table 2. Number of Cells Configuration

NUMBER OF SERIES-CONNECTED CELLS

5 6 7 8 9 10101010

SEL0 V

SEL1 V

Note:

The DC FET remains off until V

CELL

> V

UV_REL

DS2726

Configuration of Overvoltage

Threshold

The DS2726 allows the OV threshold to be set using the

overvoltage select pins. The OV threshold is configured

using the OVS0 and OVS1 pins according to Table 3.

Enabling Cell Balancing

For cell balancing to begin the DS2726 must detect a

charger. The charge-balancing configuration pin

(CBCFG) controls how the IC detects a charger. If

CBCFG is pulled to GND, balancing is enabled when

the charge-current comparator detects a charger. This

detection occurs when V

PKP

> V

VIN

+ V

CDET

. If CBCFG

is pulled to V

, cell balancing is enabled when the

SLEEP pin is driven to a logic-high state. Note that cell

balancing must be enabled and a valid cell-balancing

voltage must exist for cell balancing to occur.

Configuration of Cell-Balancing

Voltage Threshold

The DS2726 allows the cell-balancing threshold to be set

using the cell-balance select pins. The threshold is config-

ured using the CBS0 and CBS1 pins according to Table 4.

Setting the cell-balancing voltage threshold to zero dis-

ables the cell-balancing circuitry. The nominal cell-bal-

ancing voltage is never allowed a value below 3.75V.

Setting the OVS0 and OVS1 pins low while the CBS0

and CBS1 pins are high results in a cell-balancing volt-

age (V

BAL

) of 3.75V.

Nominal Cell-Balancing Voltage:

BAL

= V

– Cell-Balancing Voltage Threshold

Balancing begins when any cell’s voltage is greater

than V

BAL

. When the balancing condition is met and

cell balancing is enabled, the corresponding internal

FET (from V

to V

x-1

) is enabled, shunting a portion of

the charge current around the cell. The external resis-

tors on V00–V10 should be chosen to limit the balanc-

ing current to a maximum of 200mA. This prevents

damaging the internal cell-balancing FETs.

The DS2726 has three distinct states during balancing.

A voltage measurement state of 5/32 t

OCD

time periods

is followed by a balancing state where even numbered

cells are balanced for 123/32 t

OCD

time periods.

Another voltage measurement state of 5/32 t

OCD

time

periods then occurs. This is followed by a balancing

state where odd numbered cells are balanced for

123/32 t

OCD

time periods. This gives an average bal-

ancing current of approximately half the maximum bal-

ance current. Cell balancing terminates when all cell

voltages are greater than V

BAL

. See the

Measurement

Sequence

section.

5-Cell to 10-Cell Li+ Protector with

Cell Balancing

12 ______________________________________________________________________________________

Table 3. OV Threshold Configuration

NOMINAL OV THRESHOLD (V)

4.10 4.15 4.20 4.25 4.30 4.35 4.40 4.45 4.50

OVS0 V

OVS1 V

Table 4. Cell-Balancing Threshold Configuration

CELL-BALANCING VOLTAGE THRESHOLD (OFFSET FROM V

) (V)

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

CBS0 V

CBS1 V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

DS2726G+

Mfr. #:

Buy DS2726G+

Manufacturer:

Maxim Integrated

Description:

Battery Management 5-10 Cell Li+ Protct w/Cell Balancing

Lifecycle:

New from this manufacturer.

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DS2726G+