DS2726
5-Cell to 10-Cell Li+ Protector with
Cell Balancing
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Setting the Short-Circuit
Threshold and Delay Time
The DS2726 allows the selection of a short-circuit cur-
rent threshold. This threshold is set using a resistor
from the RSC pin to the positive terminal of the cell
stack. The RSC pin sinks 1µA (nominal). The short-cir-
cuit comparator triggers when the voltage on the SNS
pin is less than the voltage on the RSC pin. For exam-
ple, assume a 500kΩ resistor is used on RSC, along
with a DC FET with an R
DS_ON
of 10mΩ. This corre-
sponds to an RSC voltage of 500kΩ x 1µA = 0.5V.
Because the FET is 10mΩ, the short-circuit threshold is
0.5V/10mΩ = 50A:
The DS2726 allows for a delayed reaction to a short-cir-
cuit event. The short threshold must persist for the
entire delay time before the DC FET begins to turn off
(actual turn-off time varies based on the gate capaci-
tance of the DC FET; see the DC pin drive capabilities
in the
DC Electrical Characteristics
table for more
details). The short-circuit delay time is set using a
capacitor on the CSCD pin. The short-circuit delay time
can be calculated by the equation:
t
SCD
= C
SCD
x 500kΩ
Be sure to select threshold and delay times that fall
within the safe operating area of the FETs chosen for
DC and CC.
Setting the Discharge
Overcurrent Threshold
and Delay Time
The DS2726 allows the selection of a discharge over-
current threshold. This threshold is set using a resistor
from the RDOC pin to the positive terminal of the cell
stack. The RDOC pin sinks 1µA (nominal). The overcur-
rent circuit comparator triggers when the voltage on the
SNS pin is less than the voltage on the RDOC pin. For
example, assume a 200kΩ resistor is used on RDOC,
along with a DC FET with an R
DS_ON
of 10mΩ. This
corresponds to a voltage on RDOC of 200kΩ x 1µA =
0.2V. Because the FET is 10mΩ, the discharge overcur-
rent threshold is 0.2V/10mΩ = 20A:
The DS2726 allows for a delayed reaction to a dis-
charge overcurrent event. The discharge overcurrent
threshold must persist for the entire delay time before
the DC FET begins to turn off (actual turn-off time varies
based on the gate capacitance of the DC FET; see DC
pin drive capabilities in the
DC Electrical
Characteristics
table for more details). The discharge
overcurrent delay time is set using a capacitor on the
CDOCD pin. The discharge overcurrent delay can be
calculated by the equation:
t
DOCD
= C
DOCD
x 32MΩ
Be sure to select threshold and delay times that fall
within the safe operating area for the FETs chosen for
DC and CC.
If the voltage on the CDOCD pin is within approximately
1V of V
CC
or GND, the condition is considered to be a
fault, and the CC and DC outputs are disabled. This
results in a delay before enabling the FETs when the
part awakens from Sleep Mode. This delay occurs until
the voltage on CDOCD reaches an acceptable level.
This is a function of the capacitor on CDOCD. The
CDOCD startup delay is in addition to a typical regulator
startup of 100µs, and is given by the equation:
STARTUP DELAY ≈ 100µs + C
DOCD
x 1.65MΩ
Be sure to select threshold and delay times that fall
within the safe operating area for the FETs chosen for
DC and CC.
