DS2726
5-Cell to 10-Cell Li+ Protector with
Cell Balancing
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Pin Description
PIN NAME FUNCTION
1 RSC
Short-Circuit Voltage Threshold. The resistor from this pin to the positive terminal of the cell stack
selects the threshold voltage for a short-circuit condition in the discharge direction.
2 RDOC
Discharge Overcurrent Voltage Threshold. The resistor from this pin to the positive terminal of the cell
stack selects the threshold voltage for an overcurrent condition in the discharge direction.
3 V
CC
Regulator Supply Output. V
CC
supplies power to internal circuits and can be used to pull configuration
pins to V
IH
. It should be bypassed to GND with at least a 0.1μF ceramic capacitor.
4, 5
SEL0,
SEL1
Select Number of Cells in the Battery Stack. This input is a three-level input. Connect to ground or V
CC
for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table
2 for how to drive this pin for a particular number of cells.
6 CDOCD
Discharge Overcurrent Delay Time. Connect a capacitor from this pin to GND to select the amount of
time for which a discharge overcurrent condition must persist before shutting off the DC FET.
7 SLEEP
Sleep-Mode Select Input. Driving this pin to a logic-low level forces the part into the lowest power state.
The part exits Sleep Mode once a charge voltage is applied. When CBCFG is high, a logic-high on this
pin enables cell balancing.
8 CSCD
Short-Circuit Current Delay Time. Connect a capacitor from this pin to GND to select the amount of time
for which a short-circuit current condition must persist before shutting off the DC FET.
9 CBCFG
Charge-Balance Configuration Input. When this pin is at a logic-low, charge balancing is enabled if
V
PKP
> V
VIN
+ V
CDET
. When this pin is at a logic-high, charge balancing is enabled if the SLEEP pin is
at a logic-high.
10, 11
CBS0,
CBS1
Select Cell-Balancing Voltage. This input is a three-level input. Connect to ground or V
CC
for a logic-low
or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 4 for how to
drive this pin for a particular cell-balancing voltage threshold.
12, 13
OVS0,
OVS1
Select Overvoltage Threshold. This input is a three-level input. Connect to ground or V
CC
for a logic-low
or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 3 for how to
drive this pin for a particular overvoltage threshold.
14, 30 N.C. No Connection. Not internally connected.
15 GND Ground. Connect to the negative terminal of the lowest voltage cell.
16 V00 Negative Terminal Voltage Sense. Connect to the negative terminal of the 1st cell in the battery stack.
17 V01 Cell 01 Voltage Sense. Connect to the positive terminal of the 1st cell in the battery stack.
18 V02 Cell 02 Voltage Sense. Connect to the positive terminal of the 2nd cell in the battery stack.
19 V03 Cell 03 Voltage Sense. Connect to the positive terminal of the 3rd cell inf the battery stack.
20 V04 Cell 04 Voltage Sense. Connect to the positive terminal of the 4th cell in the battery stack.
21 V05 Cell 05 Voltage Sense. Connect to the positive terminal of the 5th cell in the battery stack.
22 V06 Cell 06 Voltage Sense. Connect to the positive terminal of the 6th cell in the battery stack.
23 V07 Cell 07 Voltage Sense. Connect to the positive terminal of the 7th cell in the battery stack.
24 V08 Cell 08 Voltage Sense. Connect to the positive terminal of the 8th cell in the battery stack.
25 V09 Cell 09 Voltage Sense. Connect to the positive terminal of the 9th cell in the battery stack.
26 V10 Cell 10 Voltage Sense. Connect to the positive terminal of the 10th cell in the battery stack.
27 V
IN
Connect to the Most Positive Cell Terminal
28 DC
Discharge Control Output. DC controls the gate of the discharge FET. Driven from V
IN
to V
OLDC
to turn
on and turn off the discharge FET.
