© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 1
1 Publication Order Number:
NB3N201S/D
NB3N201S, NB3N206S
3.3 V Differential Multipoint
Low Voltage M-LVDS Driver
Receiver
Description
The NB3N20xS Series are pure 3.3 V supply differential Multipoint
Low Voltage (M−LVDS) line Drivers and Receivers. Devices
NB3N201S and NB3N206S are TIA/EIA−899 compliant. NB3N201S
offers the Type 1 receiver threshold at 0.0 V. NB3N206S offers the
Type 2 receiver threshold at 0.1 V.
These devices have Type−1 and Type−2 receivers that detect the bus
state with as little as 50 mV of differential input voltage over a
common−mode voltage range of −1 V to 3.4 V. The Type−1 receivers
have near zero thresholds (±50 mV) and exhibit 25 mV of differential
input voltage hysteresis to prevent output oscillations with slowly
changing signals or loss of input. Type−2 receivers include an offset
threshold to provide a detectable voltage under open−circuit, idle−bus,
and other faults conditions.
NB3N201S and NB3N206S support Simplex or Half Duplex bus
configurations.
Features
Low−Voltage Differential 30 W to 55 W Line Drivers
and Receivers for Signaling Rates Up to 200 Mbps
Type−1 Receivers Incorporate 25 mV of Hysteresis
Type−2 Receivers Provide an Offset (100 mV)
Threshold to Detect Open−Circuit and Idle−Bus
Conditions
Meets or Exceeds the M−LVDS Standard TIA/EIA−899
for Multipoint Data Interchange
Controlled Driver Output Voltage Transition Times for
Improved Signal Quality
−1 V to 3.4 V Common−Mode Voltage Range Allows
Data Transfer With up to 2 V of Ground Noise
Bus Pins High Impedance When Disabled or VCC
1.5 V
M−LVDS Bus Power Up/Down Glitch Free
Operating range: VCC = 3.3 ±10% V( 3.0 to 3.6 V)
Operation from –40°C to 85°C.
These are Pb−Free Devices
Applications
Low−Power High−Speed Short−Reach Alternative to
TIA/EIA−485
Backplane or Cabled Multipoint Data and Clock
Transmission
Cellular Base Stations
Central−Office Switches
Network Switches and Routers
MARKING
DIAGRAMS
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
SOIC−8
D SUFFIX
CASE 751
1
8
NB20x
AYWW
G
1
8
NB20x = Specific Device Code
x = 1, 6
A = Assembly Location
Y = Year
WW = Work Week
G or G = Pb−Free Package
NB3N201S, NB3N206S
www.onsemi.com
2
Figure 1. Logic Diagram
B
GND
V
CC
DE A
RE
D
R
1
2
3
4
8
7
6
5
NB3N201S, NB3N206S
SOIC−8
Figure 2. Pinout Diagram
(Top View)
Table 1. PIN DESCRIPTION
Number Name I/O Type Open Default Description
1 R LVCMOS Output Receiver Output Pin
2 RE LVCMOS Input High Receiver Enable Input Pin (LOW = Active, HIGH = High Z
Output)
3 DE LVCMOS Input Low Driver Enable Input Pin (LOW = High Z Output, HIGH=Active)
4 D LVCMOS Input Driver Input Pin
5 GND Ground Supply pin. Pin must be connected to power supply to
guarantee proper operation.
6 A M−LVDS Input
/Output
Transceiver True Input /Output Pin
7 B M−LVDS Input
/Output
Transceiver Invert Input /Output Pin
8 VCC Power Supply pin. Pin must be connected to power supply to
guarantee proper operation.
NB3N201S, NB3N206S
www.onsemi.com
3
Table 2. DEVICE FUNCTION TABLE
TYPE 1 Receiver
(NB3N201/NB3N203)
Inputs Output
V
ID
= V
A
− V
B
RE R
V
ID
w 50 mV L H
−50 mV < V
ID
< 50 mV L ?
V
ID
−50 mV L L
X H Z
X Open Z
Open L ?
TYPE 2 Receiver
(NB3N206/NB3N207)
Inputs Output
V
ID
= V
A
− V
B
RE R
V
ID
w 150 mV L H
50 mV < V
ID
< 150 mV L ?
V
ID
50 mV L L
X H Z
X Open Z
Open L L
DRIVER
Input Enable Output
D DE A / Y B / Z
L H L H
H H H L
Open H L H
X Open Z Z
X L Z Z
H = High, L = Low, Z = High Impedance, X = Don’t Care, ? = Indeterminate

NB3N206SDG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer M-LVDS DRIVER RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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