NB3N201S, NB3N206S
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13
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak−to−peak jitter is measured using a 200 Mbps 2
15
−1 PRBS input.
Figure 14. Receiver Jitter Measurement Waveforms
Table 8. TYPE−1 RECEIVER INPUT THRESHOLD TEST VOLTAGES
Applied Voltages
Resulting Differential
Input Voltage
Resulting Common−
Mode Input Voltage
Receiver Output
VIA VIB VID VIC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.800 3.750 0.050 3.775 H
3.750 3.800 –0.050 3.775 L
–1.350 –1.400 0.050 –1.375 H
–1.400 –1.350 –0.050 –1.375 L
H = high level, L = low level, output state assumes receiver is enabled (RE = L)
Table 9. TYPE−2 RECEIVER INPUT THRESHOLD TEST VOLTAGES
Applied Voltages
Resulting Differential
Input Voltage
Resulting Common−
Mode Input Voltage
Receiver Output
(Note )
VIA VIB VID VIC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.800 3.650 0.150 3.725 H
3.800 3.750 0.050 3.775 L
–1.250 –1.400 0.150 –1.325 H
–1.350 –1.400 0.050 –1.375 L
H = high level, L = low level, output state assumes receiver is enabled (RE = L)
NB3N201S, NB3N206S
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14
Figure 15. Equivalent Input and Output Schematic Diagrams
A or B
APPLICATION INFORMATION
Receiver Input Threshold (Failsafe)
The MLVDS standard defines a type 1 and type 2 receiver.
Type 1 receivers include no provisions for failsafe and have
their differential input voltage thresholds near zero volts.
Type 2 receivers have their differential input voltage
thresholds offset from zero volts to detect the absence of a
voltage difference. The impact to receiver output by the
offset input can be seen in Table 10 and Figure 16.
Table 10. RECEIVER INPUT VOLTAGE THRESHOLD REQUIREMENTS
Receiver Type Output Low Output High
Type 1 –2.4 V VID –0.05 V 0.05 V VID 2.4 V
Type 2 –2.4 V VID 0.05 V 0.15 V VID 2.4 V
NB3N201S, NB3N206S
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15
Figure 16. Receiver Differential Input Voltage Showing Transition Regions by Type
LIVE INSERTION/GLITCH−FREE POWER UP/DOWN
The NB3N201/206 family of products provides a
glitch−free power up/down feature that prevents the
M−LVDS outputs of the device from turning on during a
power up or power down event. This is especially important
in live insertion applications, when a device is physically
connected to an M−LVDS multipoint bus and V
CC
is
ramping.
While the M−LVDS interface for these devices is glitch
free on power up/down, the receiver output structure is not.
Figure 17 shows the performance of the receiver output pin,
R (CHANNEL 2), as V
CC
(CHANNEL 1) is ramped. The
glitch on the R pin is independent of the RE voltage. Any
complications or issues from this glitch are easily resolved
in power sequencing or system requirements that suspend
operation until V
CC
has reached a steady state value.

NB3N206SDG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer M-LVDS DRIVER RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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