NB3N206SDG Datasheet NB3N201SDG, NB3N206SDG, NB3N206SDR2G | P10-P12

NB3N201S, NB3N206S

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A. All input pulses are supplied by an Agilent 8304A Stimulus System.

B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software

C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.

D. Peak−to−peak jitter is measured using a 200 Mbps 2

15−1 PRBS input.

Figure 10. Driver Jitter Measurement Waveforms

Figure 11. Receiver Voltage and Current Definitions

NB3N201S, NB3N206S

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A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 50 MHz, duty cycle = 50

±5%. C

L is a combination of a 20%−tolerance, low−loss ceramic, surface−mount capacitor and fixture capacitance within 2 cm of the

D.U.T.

B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.

Figure 12. Receiver Timing Test Circuit and Waveforms

NB3N201S, NB3N206S

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A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz, duty cycle = 50

±5%.

B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.

C. C

L is the instrumentation and fixture capacitance within 2 cm of the DUT and 20%.

Figure 13. Receiver Enable/Disable Time Test Circuit and Waveforms

Mfr. #:

Manufacturer:

ON Semiconductor

Description:

Clock Buffer M-LVDS DRIVER RECEIVER

Lifecycle:

New from this manufacturer.

Delivery:

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NB3N206SDG