ADG779
Rev. A | Page 12 of 12
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-203-AB
0.22
0.08
0.30
0.15
1.00
0.90
0.70
SEATING
PLANE
4 5 6
3 2 1
PIN 1
0.65 BSC
1.30 BSC
0.10 MAX
0.10 COPLANARITY
0.40
0.10
1.10
0.80
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
0.46
0.36
0.26
Figure 20. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description
Package
Option
Branding
1
ADG779BKS-R2 –40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 SKB
ADG779BKS-REEL –40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 SKB
ADG779BKS-REEL7 –40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 SKB
ADG779BKSZ-R2
2
–40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 S0M
ADG779BKSZ-REEL
2
–40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 S0M
ADG779BKSZ-REEL7
2
–40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 S0M
1
Brand on these packages is limited to three characters due to space constraints.
2
Z = Pb-free part.
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C02491–0–10/05(A)
