Document Number: 001-86204 Rev. *F Page 10 of 21
SRAM Write Cycle
t
WC
t
WC
Write cycle time 140 – ns
t
CA
– Chip enable active time 70 – ns
t
CW
t
SCE
Chip enable to write enable HIGH 70 – ns
t
PC
– Pre-charge time 70 – ns
t
PWC
– Page mode write enable cycle time 35 – ns
t
WP
t
PWE
Write enable pulse width 18 – ns
t
AS
t
SA
Address setup time (to CE LOW) 0 – ns
t
AH
t
HA
Address hold time (CE Controlled) 70 – ns
t
ASP
– Page mode address setup time (to WE LOW) 5 – ns
t
AHP
– Page mode address hold time (to WE LOW) 20 – ns
t
WLC
t
PWE
Write enable LOW to chip disabled 25 – ns
t
WLA
– Write enable LOW to A
14-3
change 25 – ns
t
AWH
– A
14-3
change to write enable HIGH 140 – ns
t
DS
t
SD
Data input setup time 15 – ns
t
DH
t
HD
Data input hold time 0 – ns
t
WZ
[6, 7]
t
HZWE
Write enable LOW to output HI-Z – 10 ns
t
WX
[7]
– Write enable HIGH to output driven 5 – ns
t
WS
[7, 8]
– Write enable to CE LOW setup time 0 – ns
t
WH
[7, 8]
– Write enable to CE HIGH hold time 0 – ns
AC Switching Characteristics (continued)
Over the Operating Range
Parameters
[2]
Description Min Max Unit
Cypress
Parameter
Alt Parameter
Notes
6. t
WZ
is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
7. This parameter is characterized but not 100% tested.
8. The relationship between CE
and WE determines if a CE or WE controlled write occurs.
