Document Number: 001-86204 Rev. *F Page 5 of 21
Device Operation
The FM28V020 is a bytewide F-RAM memory logically
organized as 32,768 × 8 and accessed using an
industry-standard parallel interface. All data written to the part is
immediately nonvolatile with no delay. The device offers page
mode operation, which provides high-speed access to
addresses within a page (row). Access to a different page
requires that either CE
transitions LOW or the upper address
(A
14
–A
3
) changes. See the Functional Truth Table on page 14
for a complete description of read and write modes.
Memory Operation
Users access 32,768 memory locations, each with 8 data bits
through a parallel interface. The F-RAM array is organized as
eight blocks, each having 512 rows. Each row has eight column
locations, which allow fast access in page mode operation.
When an initial address is latched by the falling edge of CE
,
subsequent column locations may be accessed without the need
to toggle CE
. When CE is deasserted HIGH, a pre-charge
operation begins. Writes occur immediately at the end of the
access with no delay. The WE
pin must be toggled for each write
operation. The write data is stored in the nonvolatile memory
array immediately, which is a feature unique to F-RAM called
NoDelay writes.
Read Operation
A read operation begins on the falling edge of CE. The falling
edge of CE
causes the address to be latched and starts a
memory read cycle if WE
is HIGH. Data becomes available on
the bus after the access time is met. When the address is latched
and the access completed, a new access to a random location
(different row) may begin while CE
is still LOW. The minimum
cycle time for random addresses is t
RC
. Note that unlike SRAMs,
the FM28V020's CE
-initiated access time is faster than the
address access time.
The FM28V020 will drive the data bus when OE
is asserted LOW
and the memory access time is met. If OE
is asserted after the
memory access time is met, the data bus will be driven with valid
data. If OE
is asserted before completing the memory access,
the data bus will not be driven until valid data is available. This
feature minimizes supply current in the system by eliminating
transients caused by invalid data being driven to the bus. When
OE
is deasserted HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM28V020, writes occur in the same interval as reads. The
FM28V020 supports both CE
and WE controlled write cycles. In
both cases, the address is latched on the falling edge of CE
.
In a CE
-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE
is LOW when the
device is activated with the chip enable. In this case, the device
begins the memory cycle as a write. The FM28V020 will not drive
the data bus regardless of the state of OE
as long as WE is LOW.
Input data must be valid when CE
is deasserted HIGH. In a
WE
-controlled write, the memory cycle begins on the falling edge
of CE
. The WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be driven if OE
is LOW; however, it will be HI-Z when WE is asserted LOW. The
CE
and WE controlled write timing cases are shown on the
page 12. In the Figure 10 on page 12 diagram, the data bus is
shown as a hi-Z condition while the chip is write-enabled and
before the required setup time. Although this is drawn to look like
a mid-level voltage, it is recommended that all DQ pins comply
with the minimum V
IH
/V
IL
operating levels.
Write access to the array begins on the falling edge of WE
after
the memory cycle is initiated. The write access terminates on the
rising edge of WE
or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE
or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access (rising edge of WE
or CE).
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Data polling, a technique used with EEPROMs
to determine if a write is complete, is unnecessary.
Page Mode Operation
The FM28V020 provides the user fast access to any data within
a row element. Each row has eight column-address locations.
Address inputs A
2
–A
0
define the column address to be
accessed. An access can start anywhere within a row and other
column locations may be accessed without the need to toggle
the CE
pin. For fast access reads, after the first data byte is
driven to the bus, the column address inputs A
2
–A
0
may be
changed to a new value. A new data byte is then driven to the
DQ pins. For fast access writes, the first write pulse defines the
first write access. While CE
is LOW, a subsequent write pulse
along with a new column address provides a page mode write
access.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. Pre-charge is
user-initiated by driving the CE
signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, t
PC
.
Pre-charge is also activated by changing the upper addresses,
A
14
–A
3
. The current row is first closed before accessing the new
row. The device automatically detects an upper order address
change, which starts a pre-charge operation. The new address
is latched and the new read data is valid within the t
AA
address
access time; see Figure 6 on page 11. A similar sequence occurs
for write cycles; see Figure 11 on page 12. The rate at which
random addresses can be issued is t
RC
and t
WC
, respectively.
