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PCA9541BS/01,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
PCA9541_7 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 24 June 2015 28 of 42
NXP Semiconductors
PCA9541
2-to-1 I
2
C-bus master selector with interrupt logic and reset
11. Limiting values
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125 C.
12. Static characteristics
Table 15. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to V
SS
(ground = 0 V).
[1]
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +7.0 V
V
I
input voltage 0.5 +7.0 V
I
I
input current 20 +20 mA
I
O
output current 25 +25 mA
I
DD
supply current 100 +100 mA
I
SS
ground supply current 100 +100 mA
P
tot
total power dissipation - 400 mW
T
stg
storage temperature 60 +150 C
T
amb
ambient temperature operating in free air 40 +85 C
Table 16. Static characteristics
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply
V
DD
supply voltage 2.3 - 5.5 V
I
DD
supply current Operating mode; no load;
V
I
=V
DD
or V
SS
; f
SCL
= 100 kHz
V
DD
=3.6V - 152 200 A
V
DD
=5.5V - 349 600 A
I
stb
standby current Standby mode; no load;
V
I
=V
DD
or V
SS
; f
SCL
= 0 kHz
V
DD
= 3.6 V - 30 80 A
V
DD
= 5.5 V - 40 100 A
V
POR
power-on reset voltage no load; V
I
=V
DD
or V
SS
[1]
-1.52.1V
Input SCL_MSTn; input/output SDA_MSTn (upstream and downstream channels)
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-6 V
I
OL
LOW-level output current V
OL
=0.4V 3 - - mA
V
OL
=0.6V 6 - - mA
I
L
leakage current V
I
=V
DD
or V
SS
1- +1A
C
i
input capacitance V
I
=V
SS
V
DD
= 2.3 V to 3.6 V - 4 5 pF
V
DD
= 3.6 V to 5.5 V - 4 6 pF
PCA9541_7 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 24 June 2015 29 of 42
NXP Semiconductors
PCA9541
2-to-1 I
2
C-bus master selector with interrupt logic and reset
[1] V
DD
must be lowered to 0.2 V in order to reset part.
Select inputs A0 to A3, INT_IN, RESET
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-6 V
I
LI
input leakage current V
I
=V
DD
or V
SS
1- +1A
C
i
input capacitance V
I
=V
SS
V
DD
= 2.3 V to 3.6 V - 2 3 pF
V
DD
= 3.6 V to 5.5 V - 2 5 pF
Pass gate
R
on
ON-state resistance V
DD
= 4.5 V to 5.5 V; V
O
=0.4V;
I
O
=15mA
41224
V
DD
= 3.0 V to 3.6 V; V
O
=0.4V;
I
O
=15mA
51430
V
DD
= 2.3 V to 2.7 V; V
O
=0.4V;
I
O
=10mA
71755
V
o(sw)
switch output voltage V
i(sw)
=V
DD
=5.0V; I
o(sw)
= 100 A- 3.6- V
V
i(sw)
=V
DD
= 4.5 V to 5.5 V;
I
o(sw)
= 100 A
2.6- 4.5V
V
i(sw)
=V
DD
=3.3V; I
o(sw)
= 100 A- 2.2- V
V
i(sw)
=V
DD
= 3.0 V to 3.6 V;
I
o(sw)
= 100 A
1.6- 2.8V
V
i(sw)
=V
DD
=2.5V; I
o(sw)
= 100 A- 1.5- V
V
i(sw)
=V
DD
= 2.3 V to 2.7 V;
I
o(sw)
= 100 A
1.1- 2.0V
I
L
leakage current V
I
=V
DD
or V
SS
1- +1A
INT0
and INT1 outputs
I
OL
LOW-level output current V
OL
=0.4V 3 - - mA
Table 16. Static characteristics
…continued
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
PCA9541_7 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 24 June 2015 30 of 42
NXP Semiconductors
PCA9541
2-to-1 I
2
C-bus master selector with interrupt logic and reset
13. Dynamic characteristics
[1] Pass gate propagation delay is calculated from the 20 typical R
on
and the 15 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH(min)
of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
Table 17. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
t
PD
propagation delay (SDA_MSTn to
SDA_SLAVE) or
(SCL_MSTn to
SCL_SLAVE)
[1]
- 0.3 - 0.3 ns
f
SCL
SCL clock frequency 0 100 0 400 kHz
f
SCL(init/rec)
SCL clock frequency
(bus initialization/bus recovery)
50 150 50 150 kHz
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - s
t
HD;STA
hold time (repeated) START condition
[2]
4.0 - 0.6 - s
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - s
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - s
t
HD;DAT
data hold time 0
[3]
3.45 0
[3]
0.9 s
t
SU;DAT
data set-up time 250 - 100 - ns
t
r
rise time of both SDA and SCL signals - 1000 20 + 0.1C
b
[4]
300 ns
t
f
fall time of both SDA and SCL signals - 300 20 + 0.1C
b
[4]
300 ns
C
b
capacitive load for each bus line - 400 - 400 pF
t
SP
pulse width of spikes that must be
suppressed by the input filter
- 50 - 50 ns
t
VD;DAT
data valid time HIGH-to-LOW
[5]
-1 - 1s
LOW-to-HIGH
[5]
- 0.6 - 0.6 s
t
VD;ACK
data valid acknowledge time - 1 - 1 s
INT
t
v(INT_IN-INTn)
valid time from pin INT_IN to pin INTn
signal
-4 - 4s
t
d(INT_IN-INTn)
delay time from pin INT_IN to pin INTn
inactive
-2 - 2s
t
w(rej)L
LOW-level rejection time INT_IN input 1 - 1 - s
t
w(rej)H
HIGH-level rejection time INT_IN input 0.5 - 0.5 - s
RESET
t
w(rst)L
LOW-level reset time 4 - 4 - ns
t
rst
reset time SDA clear 500 - 500 - ns
t
REC;STA
recovery time to START condition
[6][7]
0- 0 -ns
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PCA9541BS/01,118

Mfr. #:
Buy PCA9541BS/01,118
Manufacturer:
NXP Semiconductors
Description:
IC I2C 2:1 SELECTOR 16-HVQFN
Lifecycle:
New from this manufacturer.
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