LTC6240/LTC6241/LTC6242
25
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1M Transimpedance Amplifi er with 43nV/√Hz
Output Noise
In a normal 1M transimpedance amplifi er, like that shown
on the back page of this data sheet, the output noise density
must be at least 130nV/√Hz at room temperature. This is
true even should the op amp be perfectly noiseless, because
the 1M resistor provides 130nV/√Hz of voltage noise at
room temperature independently of the op amp.
The circuit of Figure 13 provides an overall transimpedance
gain of 1M, but it has an output noise density of only
43nV/√Hz, about 1/3 of the normal transimpedance ampli-
er. It does this by taking a higher initial transimpedance
gain of 10M and then attenuating by a factor of 10. The
transistor section provides voltage gain and works on a
54V supply voltage to guarantee adequate output swing.
By achieving an output swing of 50V before attenuation,
the circuit provides an output swing to 5V after attenu-
ation. The 10M resistor sets the gain of the TIA stage
and has a noise density of 400nV/√Hz. After attenuation,
the effective TIA gain drops to 1M while the noise fl oor
drops to 40nV/√Hz, which clearly dominates the observed
43nV/√Hz. Note the additional benefi t that the offset voltage
of the op amp is divided by 10. Worst-case output offset
for this circuit is 150µV over temperature.
Reference Buffer
Figure 14 shows the LTC6240 being utilized as a buffer
in conjunction with the LT1019 reference. The passive
R-C fi lter attenuates the reference noise and the LTC6240
provides a low noise buffer, resulting in an output noise
of 8nV/√Hz.
Figure 13. 1M Transimpedance Amplifi er with 43nV/√Hz Output Noise
Figure 14. Low Noise Reference Buffer
APPLICATIONS INFORMATION
5V
54V
–5V
–1.5V
3pF
PHOTODIODE
6241 F13
–5V
10k
+
LTC6240HV
100pF
10M
1%
0.3pF
1k
10k 2.4k
33k
MPSA06
43k
9.09k
1%
1/4W
1k
1%
V
OUT
1M GAIN
(1V/µA)
10M GAIN
(10V/µA)
MPSA06
5V
–5V
6241 F14
0.2Ω
+
LTC6240HV
1M
10µF
CERAMIC
OR FILM
8nV/√Hz
V
OUT
F
LT1019-2.5
180nV/√Hz
LTC6240/LTC6241/LTC6242
26
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DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
PACKAGE DESCRIPTION
3.00 p0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 p 0.10
(2 SIDES)
0.75 p0.05
R = 0.125
TYP
2.38 p0.10
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 0509 REV C
0.25 p 0.05
2.38 p0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.65 p0.05
(2 SIDES)
2.10 p0.05
0.50
BSC
0.70 p0.05
3.5 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
LTC6240/LTC6241/LTC6242
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DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
PACKAGE DESCRIPTION
3.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.20
TYP
4.40 ±0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHC16) DFN 1103
0.25 ± 0.05
PIN 1
NOTCH
0.50 BSC
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.20 ± 0.05
0.50 BSC
0.65 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05

LTC6240CS5#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers 1x 18MHz, L N, R2R Out, CMOS Op Amp
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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