MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
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OPERATION
Multiphase Power Conversion
The MP2932 is a multiphase VR controller for
Intel VR11 or VR10. It can be programmed for 2-,
3-, 4-, 5- or 6 channel operation for micro-
processor core supply power converters with
interleaved switching. The interleaving work of
each phase can help to reduce of ripple current
amplitude in the multiphase circuit and to reduce
input ripple current.
The MP2932 control system is based on Dual-
Edge PWM providing the fastest load response.
Under load transition condition, the MP2932 can
turn on all phase together to improve the load
transient. It can achieve excellent transient
performance and reduce the demand on the
output capacitors.
Number of Phases
The number of operational phases is determined
by internal circuitry that monitors the PWM
outputs. Normally, the MP2932 operates as a 6-
phase controller. The number of active channels
is determined by the state of PWM3, PWM4,
PWM5, and PWM6. For 2-phase operation,
connect PWM3 to VCC; similarly, PWM4 for 3-
phase, PWM5 for 4-phase, and PWM6 for 5-
phase operation. Table 1 shows the phase firing
sequence.
Table 1—Phase firing sequence
Configuration Phase Sequence
6-Phase 1 - 2 - 3 - 4 - 5 - 6
5-Phase 1 - 2 - 3 - 4 - 5
4-Phase 1 - 3 - 4 - 2
3-Phase 1 - 2 - 3
2-Phase 1 - 2
Switching Frequency
The clock frequency is set by an external resistor
R
T
connected from the FS pin to GND.
The resistor R
T
can be estimated by Equation (1).
600
SW
10
T
F
102.5
R
(1)
Where F
SW
is the switching frequency of each
phase.
Current Sensing
MP2932 has cycle by cycle current sense for fast
response. MP2932 adopts inductor DCR sensing,
or resistive sensing techniques. The sense
current, I
SEN
, is proportional to the inductor
current. The sensed current is used for current
balance, load-line regulation, and overcurrent
protection.
Inductor DCR Sensing
The MP2932 can adopt a lossless current
sensing scheme, commonly referred to as
inductor DCR sensing, as shown in Figure 2.
CURRENT
SENSE
ISEN+(n)
ISEN-(n)
RC
V (s)
V
LDCR
MP2932 INTERNAL CIRCUIT
SW
PWM
Intelli-Phase
Vin
Vin
GND
PWM(n)
I(s)
C
V
OUT
C
OUT
R
ISEN(n)
L
L
=I
R
DCR
SEN
I
L
ISEN
I
n
C
T
Figure 2—DCR Sensing Configuration
Equation (2) shows the s-domain equivalent
voltage across the inductor V
L
.

DCRLs
L
I
L
V
(2)
A simple RC network across the inductor extracts
the DCR voltage, as shown in Figure 2.
The voltage on the capacitor V
C
, can be shown to
be proportional to the channel current I
L
, see
Equation (3).


1RCs
L
IDCR1
DCR
L
s
C
V
(3)
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
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If the RC network components are selected
such that the RC time constant (=R*C) matches
the inductor time constant (=L/DCR), the
voltage across the capacitor V
C
is equal to the
voltage drop across the DCR, i.e., proportional
to the channel current.
Therefore, the current out of ISEN+ pin (I
SEN
), is
proportional to the inductor current and it can
be seen form Equation (4).
ISEN
R
DCR
L
I
SEN
I
(4)
Resistive Sensing
For accurate current sense, a current-sense
resistor R
SENSE
in series with each output
inductor can also be adopted (see Figure 3).
This technique reduces overall converter
efficiency due to the additional power loss on
R
SENSE
.
Equation (5) shows the relationship between
the channel current to the sensed current I
SEN
.
ISEN
R
SENSE
R
L
I
SEN
I
(5)
CURRENT
SENSE
I
ISEN+(n)
ISEN-(n)
MP2932 INTERNAL CIRCUIT
L
I
L
n
=I
R
R
SEN
I
L
SENSE
ISEN
R
ISEN(n)
R
SENSE V
OUT
C
OUT
C
T
Figure 3—Sense Resistor in Series with
Inductors
Channel-Current Balance
The sensed current from each active channel is
summed together and divided by the number of
active channels. The resulting average current
(I
AVG
) provides a measure of the total load
current. Channel current balance is achieved by
comparing the sensed current of each channel
to the average current to make an appropriate
adjustment to the PWM duty cycle of each
channel.
Output Voltage and Load-Line Regulation
The MP2932 uses an internal differential
remote-sense amplifier as shown in Figure 4.
The microprocessor voltage is sensed between
the VSEN and RGND pins.
The output of the error amplifier (V
COMP
) is
compared to sawtooth waveforms to generate
the PWM signals. The typical open-loop gain of
error amplifier is no less than 80dB, and the
typical open-loop bandwidth is no less than
20MHz. The PWM signals control the timing of
the MPS Intelli-phase and regulate the
converter output to the specified reference
voltage.
R C
R
C
MP2932 INTERNAL CIRCUIT
FB
ERROR AMPLIFIER
IDROOP
VDIFF
VSEN
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
V
I
REF
DAC
COMP
EXTERNAL CIRCUIT
R
V
REF
REF
FB
DROOP
V
OUT+
V
OUT-
C
C
COMP
AVG
Figure 4—Output Voltage and Load-line
Regulation
The load-line is realized by a resistor R
FB
connected between FB pin and the remote
sense output (VDIFF). As shown in Figure 4,
the average current of all active channels (I
AVG
)
flows from FB through the load-line regulation
resistor R
FB
. The resulting voltage drop across
R
FB
can be seen form Equation (6):
FB
R
AVG
I
DROOP
V
(6)
The output voltage is reduced by the droop
voltage V
DROOP
, and it is a function a load
current. It’s derived by combining Equation (6)
with the appropriate sensing current expression
defined by the current sense method.
MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
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FB
R
ISEN
R
X
R
N
OUT
I
OFS
V
REF
V
OUT
V
(7)
Where V
REF
is the reference voltage, V
OFS
is the
programmed offset voltage, I
OUT
is the total
output current of the converter, R
ISEN
is the
sense resistor connected to the ISEN+ pin, and
R
FB
is the feedback resistor, N is the active
channel number, and R
X
is the DCR, or R
SENSE
depending on the sensing method.
Therefore, the loadline is defined as:
ISEN
R
X
R
N
FB
R
LL
R
(8)
Output Voltage Offset Programming
In Figure 5, OFS pin is used to generate no-
load offset. A resistor RREF between DAC and
REF is selected, and the product (I
OFS
x R
OFS
) is
equal to the desired offset voltage.
R
C
FB
DAC
VCC
OR
GND
R
REF
OFS
GNDVCC
1.6V
0.4V
DYNAMIC
ID D/A
E/A
MP2932
REF
REF
OFS
Figure 5—Offset Voltage Programming
Connect a resistor R
OFS
between OFS to VCC
to generate a positive offset. The voltage
across it is regulated to 1.6V. This causes a
proportional current (I
OFS
) to flow into OFS. The
positive offset is:
OFS
R
REF
R1.6
OFFSET
V
(9)
Connect a resistor R
OFS
between OFS to GND
to generate a negative offset. The voltage
across it is regulated to 0.4V, and I
OFS
flows out
of OFS. The negative offset is:
OFS
R
REF
R0.4
OFFSET
V
(10)
Enable and Disable
While in shutdown mode, the PWM outputs are
held in a Hi-Z state, and the SD signal is pulled
low to assure the Intelli-phase remain off. The
following input conditions must be met to start
MP2932.
1. VCC must reach the internal power-on reset
(POR) rising threshold.
2. EN_PWR is used to coordinate the power
sequencing between VCC and another
voltage rail. The enable comparator holds
the MP2932 in shutdown until the voltage at
EN_PWR rises above 0.875V.
3. The voltage on EN_VTT must be higher than
0.875V to enable the controller. This pin is
typically connected to the output of VTT VR.
4.
10kO
910O
MP2932 INTERNAL CIRCUIT EXTERNAL CIRCUIT
VCC
EN_PWR
ENABLE
COMPARATOR
0.875V
0.875V
EN_VTT
POR
CIRCUIT
+12V
SOFT-START
AND
FAULT LOGIC
Figure 6—Power Sequencing Using
Threshold Sensitive Enable (EN) Function
When all conditions are satisfied, MP2932
begins the soft-start and ramps the output
voltage to 1.1V first. After remaining at 1.1V for
some time, MP2932 reads the ID code at ID
input pins. If the ID code is valid, MP2932 will
regulate the output to the final ID setting. If the
ID code is OFF code, MP2932 will shutdown,
and cycling VCC, EN_PWR or EN_VTT is
needed to restart.

MP2932GQK-LF-Z

Mfr. #:
Manufacturer:
Monolithic Power Systems (MPS)
Description:
Switching Controllers 6-Phase PWM Cntrlr w/8-Bit DAC code
Lifecycle:
New from this manufacturer.
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