MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
MP2932 Rev.1.02 www.MonolithicPower.com 17
4/30/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
Compensation without Load-Line
Regulation
The non load-line regulated converter is
accurately modeled as a voltage-mode
regulator with two poles at the L-C resonant
frequency and a zero at the ESR frequency. A
type-III controller, as shown in Figure 13,
provides the necessary compensation.
R
C
C
R
COMP
FB
IDROOP
VDIFF
MP2932
R
C
FB
2
C
C
1
1
Figure 13—Compensation Circuit for
MP2932 without Load-line Regulation
The first step is to choose the desired
bandwidth, f
0
, of the compensated system.
Choose a frequency high enough to assure
adequate transient performance but not higher
than 1/3 of the switching frequency. The type-III
compensator has an extra high-frequency pole,
f
HF
. A good general rule is to choose f
HF
=10f
0
,
but it can be higher if desired. Choosing f
HF
to
be lower than 10f
0
can cause problems with too
much phase shift below the system bandwidth.
Output Inductor
The output inductors and the output capacitor
bank together to form a low-pass filter
responsible for smoothing the pulsating voltage
at the phase nodes. The output filter also must
provide the transient energy until the regulator
can respond.
In high-speed converters, the output capacitor
bank is usually the most costly (and often the
largest) part of the circuit. The critical load
parameters in choosing the output capacitors
are the maximum size of the load step, ΔI; the
load-current slew rate, di/dt; and the maximum
allowable output voltage deviation under
transient loading, ΔV
MAX
. Capacitors are
characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the
output capacitors supply all of the transient
current. The output voltage will initially deviate
by an amount approximated by the voltage drop
across the ESL. As the load current increases,
the voltage drop across the ESR increases
linearly until the load current reaches its final
value. The capacitors selected must have
sufficiently low ESL and ESR so that the total
output voltage deviation is less than the
allowable maximum. Neglecting the contribution
of inductor current and regulator response, the
output voltage initially deviates by an amount in
Equation (18):
ΔIESR
dt
di
ESLΔV
(18)
The filter capacitor must have sufficiently low
ESL and ESR so that ΔV < ΔV
MAX
.
The ESR of the bulk capacitors also creates the
majority of the output voltage ripple. As the bulk
capacitors sink and source the inductor AC
ripple current, a voltage develops across the
bulk-capacitor ESR. Thus, once the output
capacitors are selected, the maximum
allowable ripple voltage, V
P-P(MAX)
determines
the lower limit on the inductance.
MAXP-P
V
IN
V
s
f
OUT
V
OUT
NV-
IN
V
ESRL
(19)
Since the capacitors are supplying a decreasing
portion of the load current while the regulator
recovers from the transient, the capacitor
voltage becomes slightly depleted. The output
inductors must be capable of assuming the
entire load current before the output voltage
decreases more than ΔV
MAX
. This places an
upper limit on inductance.
Input Capacitor
The input capacitors are responsible for
sourcing the AC component of the input current
flowing into the upper MOSFETs. Their RMS
current capacity must be sufficient to handle the
AC component of the current drawn by the
upper MOSFETs which is related to duty cycle
and the number of active phases.
