LTC4253CGN#PBF Datasheet LTC4253CGN#PBF, LTC4253IGN#PBF, LTC4253CGN#TRPBF | P19-P21

LTC4253/LTC4253A

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APPLICATIONS INFORMATION

TIMER commences charging C

(trace 4) while the analog

current limit loop maintains the fault current at 100mV/R

which in this case is 5A (trace 2). Note that the backplane

voltage (trace 1) sags under load. Timer pull-up is accel-

erated by V

OUT

. When C

reaches 4V, GATE turns off, the

PWRGD signals pull high, the load current drops to zero

and the backplane rings up to over 100V. The transient

associated with the GATE turn-off can be controlled with

a snubber to reduce ringing and a transient voltage sup-

pressor (such as Diodes Inc. SMAT70A) to clip off large

spikes. The choice of RC for the snubber is usually done

experimentally. The value of the snubber capacitor is usu-

ally chosen between 10 to 100 times the MOSFET C

OSS

The value of the snubber resistor is typically between 3Ω

to 100Ω.

A low impedance short on one card may influence the

behavior of others sharing the same backplane. The ini-

tial glitch and backplane sag as seen in Figure 5 trace1,

can rob charge from output capacitors on the adjacent

card. When the faulty card shuts down, current flows in

to refresh the capacitors. If LTC4253/LTC4253A are used

by the other cards, they respond by limiting the inrush

current to a value of V

ACL

. If C

is sized correctly, the

capacitors will recharge long before C

times out.

Figure 5. Output Short-Circuit Behavior of LTC4253

Sense

The SENSE pin is monitored by the circuit breaker (CB)

comparator, the analog current limit (ACL) amplifier, and

the fast current limit (FCL) comparator. Each of these three

measures the potential of SENSE relative to V

. When

SENSE exceeds 50mV, the CB comparator activates the

200µA TIMER pull-up. At 100mV (60mV for the LTC4253A)

the ACL amplifier servos the MOSFET current, and at

200mV the FCL comparator abruptly pulls GATE low in

an attempt to bring the MOSFET current under control. If

any of these conditions persists long enough for TIMER to

charge C

to 4V (see Equation3), the LTC4253/LTC4253A

shut down and pull GATE low.

If the SENSE pin encounters a voltage greater than V

ACL

the ACL amplifier will servo GATE downwards in an attempt

to control the MOSFET current. Since GATE overdrives the

MOSFET in normal operation, the ACL amplifier needs time

to discharge GATE to the threshold of the MOSFET. For a

mild overload the ACL amplifier can control the MOSFET

current, but in the event of a severe overload the current

may overshoot. At SENSE = 200mV the FCL comparator

takes over, quickly discharging the GATE pin to near V

potential. FCL then releases, and the ACL amplifier takes

over. All the while TIMER is running. The effect of FCL is

to add a nonlinear response to the control loop in favor

of reducing MOSFET current.

Owing to inductive effects in the system, FCL typically

overcorrects the current limit loop, and GATE undershoots.

A zero in the loop (resistor R

in series with the gate

capacitor) helps the ACL amplifier to recover.

SHORT-CIRCUIT OPERATION

Circuit behavior arising from a load side low impedance

short is shown in Figure 5. Initially the current overshoots

the analog current limit level of V

SENSE

=200mV (trace 2)

as the GATE pin works to bring V

under control (trace3).

The overshoot glitches the backplane in the negative direc-

tion and when the current is reduced to 100mV/R

, the

backplane responds by glitching in the positive direction.

GATE

0.5ms

10V

SENSE

0.5ms

200mV

–48RTN

0.5ms

50V

TIMER

0.5ms

4253 F05

SUPPLY RING OWING

TO CURRENT OVERSHOOT

SUPPLY RING OWING

TO MOSFET TURN-OFF

ONSET OF OUTPUT

SHORT-CIRCUIT

FAST CURRENT

LIMIT

TIMER

RAMP

LATCH OFF

TRACE 1

TRACE 2

TRACE 3

TRACE 4

ANALOG

CURRENT LIMIT

LTC4253/LTC4253A

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MOSFET SELECTION

The external MOSFET switch must have adequate safe op-

erating area (SOA) to handle short-circuit conditions until

TIMER times out. These considerations take precedence

over DC current ratings. A MOSFET with adequate SOA for

a given application can always handle the required current

but the opposite may not be true. Consult the manufacturer’s

MOSFET data sheet for safe operating area and effective

transient thermal impedance curves.

MOSFET selection is a 3-step process by assuming the

absence of soft-start capacitor. First, R

is calculated and

then the time required to charge the load capacitance is

determined. This timing, along with the maximum short-

circuit current and maximum input voltage, defines an

operating point that is checked against the MOSFET’s

SOA curve.

To begin a design, first specify the required load current

and Ioad capacitance, I

and C

. The circuit breaker cur-

rent trip point (V

) should be set to accommodate

the maximum load current. Note that maximum input

current to a DC/DC converter is expected at V

SUPPLY(MIN)

is given by:

CB(MIN)

L(MAX)

(8)

where V

CB(MIN)

= 40mV (45mV for the LTC4253A) repre-

sents the guaranteed minimum circuit breaker threshold.

During the initial charging process, the LTC4253/LTC4253A

may operate the MOSFET in current limit, forcing (V

ACL

)

between 80mV to 120mV (V

ACL

is 54mV to 66mV for the

LTC4253A) across R

. The minimum inrush current is

given by:

INRUSH(MIN)

ACL(MIN)

(9)

Maximum short-circuit current limit is calculated using

the maximum V

SENSE

. This gives

SHORTCIRCUIT(MAX)

ACL(MAX)

(10)

The TIMER capacitor C

must be selected based on the

slowest expected charging rate; otherwise TIMER might

time out before the load capacitor is fully charged. A value

for C

is calculated based on the maximum time it takes

the load capacitor to charge. That time is given by:

CL(CHARGE)

C • V

• V

SUPPLY(MAX)

INRUSH(MIN)

(11)

The maximum current flowing in the DRAIN pin is given by:

DRN(MAX)

SUPPLY(MAX)

− V

DRNCL

(12)

Approximating a linear charging rate, I

DRN

drops from

DRN(MAX)

to zero, the I

DRN

component in Equation (3)

can be approximated with 0.5 • I

DRN(MAX)

. Rearranging

the equation, TIMER capacitor C

is given by:

CL(CHARGE)

• (200µA + 4 • I

DRN(MAX)

)

(13)

Returning to Equation (3), the TIMER period is calcu-

lated and used in conjunction with V

SUPPLY(MAX)

and

SHORTCIRCUIT(MAX)

to check the SOA curves of a prospec-

tive MOSFET.

As a numerical design example for the LTC4253, consider

a 30W load, which requires 1A input current at 36V. If

SUPPLY(MAX)

= 72V and C

= 100µF, R

= 1MΩ, Equation

(8) gives R

=40mΩ; Equation (13) gives C

= 414nF.

To account for errors in R

, C

, TIMER current (200µA),

TIMER threshold (4V), R

, DRAIN current multiplier and

DRAIN voltage clamp (V

DRNCL

), the calculated value should

be multiplied by 1.5, giving the nearest standard value of

=680nF.

If a short-circuit occurs, a current of up to 120mV/40mΩ=3A

will flow in the MOSFET for 6.3ms as dictated by C

= 680nF

in Equation (3). The MOSFET must be selected based on

this criterion. The IRF530S can handle 100V and 3A for

10ms and is safe to use in this application.

APPLICATIONS INFORMATION

LTC4253/LTC4253A

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Computing the maximum soft-start capacitor value during

soft-start to a load short is complicated by the nonlinear

MOSFET’s SOA characteristics and the R

response.

An overconservative but simple approach begins with the

maximum circuit breaker current, given by:

CB(MAX)

(14)

where V

CB(MAX)

is 60mV (55mV for the LTC4253A).

From the SOA curves of a prospective MOSFET, determine

the time allowed, t

SOA(MAX)

. C

is given by:

SOA(MAX)

0.916 • R

for the LTC4253

SOA(MAX)

2.48 • R

for the LTC4253A

(15)

In the above example, 60mV/40mΩ gives 1.5A. t

SOA

for

the IRF530S is 40ms. From Equation (15), C

= 437nF.

Actual board evaluation showed that C

= 100nF was ap-

propriate. The ratio ( R

•

) to t

CL(CHARGE)

is a good

gauge as large ratios may result in the time-out period

expiring prematurely. This gauge is determined empirically

with board level evaluation.

SUMMARY OF DESIGN FLOW

To summarize the design flow, consider the application

shown in Figure 3 for the LTC4253A. It was designed for

80W and C

=100µF.

Calculate maximum load current: 80W/43V = 1.86A;

allowing for 83% converter efficiency, I

IN(MAX)

= 2.2A.

Calculate R

: from Equation (8) R

= 20mΩ.

Calculate I

SHORT-CIRCUIT(MAX)

: from Equation (10)

SHORTCIRCUIT(MAX)

= 3.3A.

Select a MOSFET that can handle 3.3A at 71V: IRF530S.

Calculate C

: from Equation (13) C

= 302nF. Select

 = 680nF, which gives the circuit breaker time-out

period t

MAX

= 5.9ms.

Consult MOSFET SOA curves: the IRF530S can handle 3.3A

at 100V for 8.3ms, so it is safe to use in this application.

Calculate C

: using Equations (14) and (15) select

=33nF.

FREQUENCY COMPENSATION

The LTC4253 typical frequency compensation network

for the analog current limit loop is a series R

(10Ω)

and C

connected from GATE to V

. Figure 6 depicts the

relationship between the compensation capacitor C

and

the MOSFET’s C

ISS

. The line in Figure 6 is used to select

a starting value for C

based upon the MOSFET’s C

ISS

specification. Optimized values for C

are shown for sev-

eral popular MOSFETs. Differences in the optimized value

of C

versus the starting value are small. Nevertheless,

compensation values should be verified by board level

short-circuit testing.

As seen in Figure 5, at the onset of a short-circuit event,

the input supply voltage can ring dramatically due to series

inductance. If this voltage avalanches the MOSFET, current

continues to flow through the MOSFET to the output. The

analog current limit loop cannot control this current flow

and therefore the loop undershoots. This effect cannot be

eliminated by frequency compensation. A Zener diode is

required to clamp the input supply voltage and prevent

MOSFET avalanche.

Figure 6. Recommended Compensation

Capacitor C

vs MOSFET C

ISS

for the LTC4253

MOSFET C

ISS

(pF)

COMPENSATION CAPACITOR C

(nF)

4253 F06

2000

4000

6000

8000

IRF530

IRF540

IRF740

IRF3710

NTY100N10

APPLICATIONS INFORMATION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

LTC4253CGN#PBF

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Analog Devices Inc.

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