LTC4253/LTC4253A
22
425353aff
For more information www.linear.com/4253
APPLICATIONS INFORMATION
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4253/
LTC4253A’s V
EE
and SENSE pins are strongly recom-
mended. The drawing in Figure 7 illustrates the correct way
of making connections between the LTC4253/LTC4253A
and the sense resistor. PCB layout should be balanced
and symmetrical to minimize wiring errors. In addition,
the PCB layout for the sense resistor should include good
thermal management techniques for optimal sense resistor
power dissipation.
Figure 7. Making PCB Connections to the Sense Resistor
TIMING WAVEFORMS
System Power-Up
Figure 8 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
V
OUT
and DRAIN. V
IN
and the PWRGD signals follow at
a slower rate as set by the V
IN
bypass capacitor. At time
point 2, V
IN
exceeds V
LKO
and the internal logic checks for
UV > V
UVHI
(V
UV
for the LTC4253A), OV < V
OVLO
(V
OV
–
V
OVHST
for the LTC4253A), RESET < 0.8V, GATE < V
GATEL
,
SENSE < V
CB
, SS < 20 • V
OS
, and TIMER < V
TMRL
. When
all conditions are met, initial timing starts and the TIMER
capacitor is charged by a 5µA current source pull-up. At
time point 3, TIMER reaches the V
TMRH
threshold and
the initial timing cycle terminates. The TIMER capacitor
is quickly discharged. At time point 4, the V
TMRL
thresh-
old is reached and the conditions of GATE < V
GATEL
,
SENSE<V
CB
and SS < 20 • V
OS
must be satisfied before
the GATE start-up cycle begins. SS ramps up as dictated
by R
SS
• C
SS
(as in Equation 6); GATE is held low by the
analog current limit (ACL) amplifier until SS crosses 20 •
V
OS
. Upon releasing GATE, 50µA sources into the external
MOSFET gate and compensation network. When the GATE
voltage reaches the MOSFET’s threshold, current flows
into the load capacitor at time point 5. At time point 6,
load current reaches SS control level and the analog cur-
rent limit loop activates. Between time points 6 and 8, the
GATE voltage is servoed, the SENSE voltage is regulated
at V
ACL
(t) (Equation 7) and soft-start limits the slew rate
of the load current. If the SENSE voltage (V
SENSE
– V
EE
)
reaches the V
CB
threshold at time point 7, circuit breaker
TIMER activates. The TIMER capacitor, C
T
, is charged by
a (200µA+8•I
DRN
) current pull-up. As the load capaci-
tor nears full charge, load current begins to decline. At
time point 8, the load current falls and the SENSE voltage
drops below V
ACL
(t). The analog current limit loop shuts
off and the GATE pin ramps further. At time point 9, the
SENSE voltage drops below V
CB
, the fault TIMER ends,
followed by a 5µA discharge cycle (cool-off). The duration
between time points 7 and 9 must be shorter than one
circuit breaker delay to avoid fault time-out during GATE
ramp-up. When GATE ramps past the V
GATEH
threshold
at time pointA, PWRGD1 pulls low. At time point B, GATE
reaches its maximum voltage as determined by V
IN
. At time
point A, SQTIMER starts its ramp-up to 4V. Having satis-
fied the requirement that PWRGD1 is low for more than
one t
SQT
, PWRGD2 pulls low after EN2 pulls high above
the V
IH
threshold at time point C. This sets off the second
SQTIMER ramp-up. Having satisfied the requirement that
PWRGD2 is low for more than one t
SQT
, PWRGD3 pulls
low after EN3 pulls high at time point D.
W
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
SENSE RESISTOR
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
TO
SENSE
TO
V
EE
4253 F07
