LTC2430/LTC2431
23
24301f
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The C
PAR
capacitor
includes the LTC2430/LTC2431 pin capacitance (5pF typi-
cal) plus the capacitance of the test fixture used to obtain
the results shown in Figures 13 and 14. A careful imple-
mentation can bring the total input capacitance (C
IN
+
C
PAR
) closer to 5pF thus achieving better performance
than the one predicted by Figures 13 and 14. For simplic-
ity, two distinct situations can be considered.
F
or relatively small values of input capacitance (C
IN
<
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for C
IN
will deteriorate the converter offset and gain
performance without significant benefits of signal filter-
ing and the user is advised to avoid them. Nevertheless,
when small values of C
IN
are unavoidably present as
parasitics of input multiplexers, wires, connectors or
sensors, the LTC2430 or LTC2431 can maintain its excep-
tional accuracy while operating with relative large values
of source resistance as shown in Figures 13 and 14. These
measured results may be slightly different from the first
order approximation suggested earlier because they in-
clude the effect of the actual second order input network
together with the nonlinear settling process of the input
amplifiers. For small C
IN
values, the settling on IN
+
and
IN
–
occurs almost independently and there is little benefit
in trying to match the source impedance for the two pins.
Larger values of input capacitors (C
IN
> 0.01µF) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When F
O
= LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 21.6MΩ which will
generate a gain error of approximately 0.023ppm for each
ohm of source resistance driving IN
+
or IN
–
. When F
O
=
HIGH (internal oscillator and 50Hz notch), the typical
differential input resistance is 26MΩ which will generate
a gain error of approximately 0.019ppm for each ohm of
source resistance driving IN
+
or IN
–
. When F
O
is driven by
an external oscillator with a frequency f
EOSC
(external
conversion clock operation), the typical differential input
resistance is 3.3 • 10
12
/f
EOSC
Ω and each ohm of source
resistance driving IN
+
or IN
–
will result in 0.15 • 10
–6
•
f
EOSC
ppm gain error. The effect of the source resistance on
the two input pins is additive with respect to this gain error.
APPLICATIO S I FOR ATIO
WUUU
Figure 12. An RC Network at IN
+
and IN
–
Figure 13. +FS Error vs R
SOURCE
at IN
+
or IN
–
(Small C
IN
)
Figure 14. –FS Error vs R
SOURCE
at IN
+
or IN
–
(Small C
IN
)
C
IN
2431 F12
V
INCM
+ 0.5V
IN
R
SOURCE
C
PAR
≅20pF
C
IN
V
INCM
– 0.5V
IN
R
SOURCE
C
PAR
≅20pF
IN
+
IN
–
LTC2430/
LTC2431
R
SOURCE
(Ω)
1 10 100 1k 10k 100k
+FS ERROR (ppm)
2431 F13
50
40
30
20
10
0
–10
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 3.75V
V
IN
–
= 1.25V
F
O
= GND
T
A
= 25°C
C
IN
=
0.01µF
C
IN
=
0pF
C
IN
=
0.001µF
C
IN
=
100pF
R
SOURCE
(Ω)
1
–50
–FS ERROR (ppm)
–40
–30
–20
–10
0
10
10 100 1k 10k
2431 F14
100k
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 1.25V
V
IN
–
= 3.75V
F
O
= GND
T
A
= 25°C
C
IN
=
0.01µF
C
IN
=
0pF
C
IN
=
0.001µF
C
IN
=
100pF
