Document Number: 001-49315 Rev. *E Page 10 of 14
Ordering Code Definitions
Truth Table
CE OE WE BLE BHE
I/O
0
–I/O
7
I/O
8
–I/O
15
Mode Power
H X X X X High Z High Z Power-down Standby (I
SB
)
L L H L L Data Out Data Out Read all bits Active (I
CC
)
L L H L H Data Out High Z Read lower bits only Active (I
CC
)
L L H H L High Z Data Out Read upper bits only Active (I
CC
)
L X L L L Data In Data In Write all bits Active (I
CC
)
L X L L H Data In High Z Write lower bits only Active (I
CC
)
L X L H L High Z Data In Write upper bits only Active (I
CC
)
L H H X X High Z High Z Selected, outputs disabled Active (I
CC
)
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
10 CY7C10612DV33-10ZSXI 51-85160 54-pin TSOP II (Pb-free) Industrial
Temperature Grade:
I = Industrial
Pb-free
Package Type:
ZS = 54-pin TSOP II
Speed Grade: 10 ns
Voltage range: 3 V to 3.6 V
Process Technology: C9, 90 nm
Single chip enable
Bus width = × 16
Density = 16-Mbit
Fast asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CY
10 ZS
7
C
1
06
X
1
I
-
V332 D
