Document Number: 001-49315 Rev. *E Page 6 of 14
AC Switching Characteristics
Over the Operating Range
Parameter
[4]
Description
-10
Unit
Min Max
Read Cycle
t
power
V
CC
(typical) to the first access
[5]
100 – s
t
RC
Read cycle time 10 – ns
t
AA
Address to data valid – 10 ns
t
OHA
Data hold from address change 3 – ns
t
ACE
CE LOW to data valid – 10 ns
t
DOE
OE LOW to data valid – 5 ns
t
LZOE
OE LOW to low Z 1 – ns
t
HZOE
OE HIGH to high Z
[6]
–5ns
t
LZCE
CE LOW to low Z
[6]
3–ns
t
HZCE
CE HIGH to high Z
[6]
–5ns
t
PU
CE LOW to power-up
[7]
0–ns
t
PD
CE HIGH to power-down
[7]
–10ns
t
DBE
Byte enable to data valid – 5 ns
t
LZBE
Byte enable to low Z 1 – ns
t
HZBE
Byte disable to high Z – 5 ns
Write Cycle
[8, 9]
t
WC
Write cycle time 10 – ns
t
SCE
CE LOW to write end 7 – ns
t
AW
Address setup to write end 7 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width 7–ns
t
SD
Data setup to write end 5.5 – ns
t
HD
Data hold from write end 0 – ns
t
LZWE
WE HIGH to low Z
[6]
3–ns
t
HZWE
WE LOW to high Z
[6]
–5ns
t
BW
Byte enable to end of write 7 – ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading shown in part a) of Figure 2 on page 5, unless specified otherwise.
5. t
POWER
gives the minimum amount of time that the power supply is at typical V
CC
values until the first memory access is performed.
6. t
HZOE
, t
HZCE
, t
HZWE
, t
HZBE
, t
LZOE
, t
LZCE
, t
LZWE
, and t
LZBE
are specified with a load capacitance of 5 pF as in (b) of Figure 2 on page 5. Transition is measured 200 mV from steady
state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal write time of the memory is defined by the overlap of WE
, CE
= V
IL
. Chip enable must be active and WE and byte enables must be LOW to initiate a write,
and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 2 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
