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CY7C10612DV33-10ZSXIT

P1-P3P4-P6P7-P9P10-P12P13-P15
CY7C10612DV33
Document Number: 001-49315 Rev. *E Page 3 of 14
Selection Guide
Description -10 Unit
Maximum Access Time 10 ns
Maximum Operating Current 175 mA
Maximum CMOS Standby Current 25 mA
Pin Configuration
Figure 1. 54-pin TSOP II (Top View)
[1]
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
I/O
11
18
17
20
19
23
28
25
24
22
21
27
26
V
SS
I/O
10
I/O
12
V
CC
I/O
13
I/O
14
V
SS
A
16
A
17
A
11
A
12
A
13
A
14
I/O
0
A
15
I/O
7
I/O
9
V
CC
I/O
8
I/O
15
A
19
A
4
A
3
A
2
A
1
CE
V
CC
WE
NC
BLE
NC
V
SS
OE
A
8
A
7
A
6
A
5
A
0
NC
A
9
BHE
A
10
10
A
18
46
45
47
50
49
48
51
54
53
52
I/O
2
I/O
1
I/O
3
V
SS
V
CC
V
SS
I/O
6
I/O
5
V
CC
I/O
4
Note
1. NC pins are not connected on the die.
CY7C10612DV33
Document Number: 001-49315 Rev. *E Page 4 of 14
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on
V
CC
Relative to GND
[2]
...............................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State
[2]
................................–0.5 V to V
CC
+ 0.5 V
DC Input Voltage
[2]
............................–0.5 V to V
CC
+ 0.5 V
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................> 2001 V
Latch Up Current ...................................................> 200 mA
Operating Range
Range Ambient Temperature V
CC
Industrial –40 C to +85 C 3.3 V 0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
-10
Unit
Min Max
V
OH
Output HIGH voltage Min V
CC
, I
OH
= –4.0 mA 2.4 – V
V
OL
Output LOW voltage Min V
CC
, I
OL
= 8.0 mA – 0.4 V
V
IH
Input HIGH voltage 2.0 V
CC
+ 0.3 V
V
IL
Input LOW voltage
[2]
–0.3 0.8 V
I
IX
Input leakage current GND V
IN
V
CC
–1 +1 A
I
OZ
Output leakage current GND V
OUT
V
CC
, Output disabled –1 +1 A
I
CC
V
CC
operating supply current V
CC
= Max, f = f
MAX
= 1/t
RC,
I
OUT
= 0 mA,
CMOS levels
–175mA
I
SB1
Automatic CE power-down
current – TTL inputs
Max V
CC
, CE V
IH
,
V
IN
V
IH
or V
IN
V
IL
, f = f
MAX
–30mA
I
SB2
Automatic CE power-down
current – CMOS Inputs
Max V
CC
, CE V
CC
– 0.3 V,
V
IN
V
CC
– 0.3 V, or V
IN
0.3 V, f = 0
–25mA
Capacitance
Parameter
[3]
Description Test Conditions 54-pin TSOP II Unit
C
IN
Input capacitance T
A
= 25 C, f = 1 MHz, V
CC
= 3.3 V 6 pF
C
OUT
I/O capacitance 8pF
Thermal Resistance
Parameter
[3]
Description Test Conditions 54-pin TSOP II Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four layer printed circuit
board
24.18 C/W
JC
Thermal resistance
(junction to case)
5.40 C/W
Note
2. V
IL(min)
= –2.0 V and V
IH(max)
= V
CC
+ 2 V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
CY7C10612DV33
Document Number: 001-49315 Rev. *E Page 5 of 14
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
[4]
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
3.3 V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
(b)
R1 317
R2
351
RISE TIME:
FALL TIME:
> 1 V/ns
(c)
OUTPUT
50
Z
0
= 50
V
TH
= 1.5 V
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
HIGH Z CHARACTERISTICS:
(a)
> 1 V/ns
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
[5]
Max Unit
V
DR
V
CC
for data retention 2 – – V
I
CCDR
Data retention current V
CC
= 2 V, CE V
CC
– 0.2 V,
V
IN
V
CC
– 0.2 V or V
IN
0.2 V
––25mA
t
CDR
[6]
Chip deselect to data retention time 0 – – ns
t
R
[7]
Operation recovery time t
RC
––ns
Data Retention Waveform
Figure 3. Data Retention Waveform
3.0 V3.0 V
t
CDR
V
DR
> 2 V
DATA RETENTION MODE
t
R
CE
V
CC
Notes
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0 V). 100 s (t
power
) after reaching the minimum operating
V
DD
, normal SRAM operation begins including reduction in V
DD
to the data retention (V
CCDR
, 2.0 V) voltage.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
50 s or stable at V
CC(min.)
50 s.
P1-P3P4-P6P7-P9P10-P12P13-P15

CY7C10612DV33-10ZSXIT

Mfr. #:
Buy CY7C10612DV33-10ZSXIT
Manufacturer:
Cypress Semiconductor
Description:
SRAM 16Mb 10ns 3.3V 1Mx16 Fast Async SRAM
Lifecycle:
New from this manufacturer.
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