OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

DS2181AN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
DS2181A
13 of 32
TSD INPUT TIMING Figure 7
CAS OUTPUT FORMAT IN TIMESLOT 16 Figure 8
FRAME 0
1
FRAME 1 FRAME 15
0000XYXX ABCD for
Timeslot 1
ABCD for
timeslot 17
ABCD for
Timeslot 15
ABCD for
Timeslot 31
NOTE:
1. Timeslot 16 of frame 0 is reserved for the multiframe alignment word (0000), distant multiframe
alarm (Y) and extra bits (X-XX).
TINR: TRANSMIT INTERNATIONAL AND NATIONAL REGISTER Figure 9
(MSB) (LSB)
INB - TRA NB4 NB5 NB6 NB7 NB8
SYMBOL POSITION NAME AND DESCRIPTION
INB TINR.7 International Bit. Inserted into the outgoing data stream when
TCR.4 = 1.
- TINR.6 Reserved; must be 0 for proper operation.
TRA TINR.5
Transmit Remote Alarm
0 = Normal operation; bit 3 of timeslot 0 in non-alignment frame
clear.
1 = Alarm condition; bit 3 of timeslot 0 in non-align frames set.
NB4 TINR.4 Transmit National Bits. Inserted into the outgoing data stream at
TPOS and TNEG when TCR.3 = 1.
NB5 TINR.3
NB6 TINR.2
NB7 TINR.1
NB8 TINR.0
TRANSMIT INTERNATIONAL AND NATIONAL DATA
Bit 1 of timeslot 0 in all frames is known as the international bit. When TCR.4 = 1, the transmitted
international bit is sourced from TINR.7. When TCR.4 = 0, the transmitted international bit is sampled at
TIND during the first bit period of each frame. The international bit positions in all outgoing frames
except 13 and 15 are replaced by CRC4 code words and the CRC4 multiframe alignment signal when
CCR.3 = 1.
DS2181A
14 of 32
Bits 4 through 8 of timeslot 0 in non-align frames are reserved for national use. When TCR.3 = 1, the
transmitted national bits are sourced from register locations TINR.4 through TINR.0. If TCR.3 = 0, the
national bits are sampled at TIND during bit times 4 through 8 of timeslot 0 in non-align frames.
Reserved bit positions in the TINR must be set to 0 when written; those bits can be 0 or 1 when read.
TXR: TRANSMIT EXTRA REGISTER Figure 10
(MSB) (LSB)
- - - - XB1 TDMA XB2 XB3
SYMBOL POSITION NAME AND DESCRIPTION
- TXR.7 Reserved; must be 0 for proper operation.
- TXR.6 Reserved; must be 0 for proper operation.
- TXR.5 Reserved; must be 0 for proper operation.
- TXR.4 Reserved; must be 0 for proper operation.
XB1 TXR.3
Extra Bit 1
TDMA TXR.2
Transmit Distant Multiframe Alarm
0 = Normal operation; bit 6 of timeslot 16 in frame 0 clear.
1 = Alarm condition; bit 6 of timeslot 16 in frame 0 set.
XB2 TXR.1
Extra Bit 2
XB3 TXR.0
Extra Bit 3
TRANSMIT EXTRA DATA
In the CAS mode, timeslot 16 of frame 0 contains the multiframe alignment pattern, extra bits and the
distant multiframe alarm. When CAS is enabled (TCR.5 = 0), the extra bits are sourced from TXR.0,
TXR.1 and TXR.3 (TCR.2 = 1) or the extra bits are sampled externally at TXD during the extra bit time
(TCR.2 = 0). The extra bits, alignment pattern and alarm signal are not utilized in the CCS mode (TCR.5
= 1); input TSER overwrites all timeslot 16 bit positions.
Reserved bit positions in the TXR must be set to 0 when written; those bits can be 0 or 1 when read.
TIR1 - TIR4: TRANSMIT IDLE REGISTERS Figure 11
(MSB) (LSB)
TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0
1
TIR1
TS15 TS14 TS13 TS12 TS11 TS10 TS9 TS8 TIR2
TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16
1
TIR3
TS31 TS30 TS29 TS28 TS27 TS26 TS25 TS024 TIR4
SYMBOL POSITION NAME AND DESCRIPTION
TS31 TIR4.7
Transmit Idle Registers
TS0 TIR1.0 Each of these bit positions represents a timeslot in the outgoing
stream at TPOS and TNEG; when set, the contents of that timeslot
are forced to idle code (11010101).
NOTE:
1. TS0 and TS16 are not affected by the idle register.
DS2181A
15 of 32
TRANSMIT TIMING
A low-high transition at TMSYNC once per multiframe (every 2 milliseconds) or at a multiple of the
multiframe rate establishes outgoing CAS and/or CRC4 multiframe alignment. Output TMO indicates
that alignment. A low-high transition at TFSYNC at the frame rate (125 us) or at a multiple of the frame
rate establishes the outgoing frame position. Output TAF indicates that alignment. TMSYNC and/or
TFSYNC can be tied low by the user, in which case the arbitrary frame and multiframe alignment
established by the device will be indicated at TMO and TAF.
Output TAF also indicates frames containing the frame alignment signal. Those frames can be even or
odd numbering frames of the outgoing CAS multiframe (CCR.6).
TRANSMIT MULTIFRAME TIMING Figure 12
NOTES:
1. Alignment frames are even frames of the CAS and/or CRC4 multiframes (CCR.6 = 0).
2. Alignment frames are odd frames of the CAS multiframe (CCR.6 = 1).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

DS2181AN

Mfr. #:
Buy DS2181AN
Manufacturer:
Maxim Integrated
Description:
Telecom Interface ICs CEPT Primary Rate Transceiver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet