DS2181A
4 of 32
NOTES:
1. These output status pins are only available on the DS2181AQ.
2. If the TEST pin is tied low and CCR.1=0, then these pins will be tri–stated.
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 2B
PIN SYMBOL TYPE DESCRIPTION
21 RRA O
Receive Remote Alarm. Transitions high when alarm detected;
returns low when alarm cleared.
22 RMDA O
Receive Distant Multiframe Alarm. Transitions high when alarm
detected; returns low when alarm cleared.
23 RAF O
Receive Alignment Frame. High during frames containing the frame
alignment signal, low otherwise.
24 RCLK I
Receive Clock. 2.048 MHz primary clock.
25 RCHCLK O
Receive Channel Clock. 256 kHz clock, identifies timeslot
boundaries; useful for serial-to-parallel conversion of channel data.
26 RSER O
Receive Channel Clock. 256 kHz clock, identifies timeslot
boundaries; useful for serial-to-parallel conversion of channel data.
27 RFSYNC O
Receive Frame Sync. Trailing edge indicates start of frame.
28 RMSYNC O
Receive Multiframe Sync. Low-high transition indicates start of
CAS multiframe; held high during frame 0.
29 RSD O
Receive Signaling Data. Extracted timeslot 16 data; updated on
rising edge of RCLK.
30 RSTS O
Receive Signaling Timeslot. High during timeslot 16 of every frame,
low otherwise.
31 RCSYNC O
Receive CRC4 Sync. Low-high transition indicates start of CRC4
multiframe; held high during CRC4 frames 0 through 7 and held low
during frames 8 through 15.
33
RST
I
Reset. Must be asserted during device power-up and when changing
to/from the hardware mode.
34
35
RPOS
RNEG
I
Receive Bipolar Data. Sampled on falling edges of RCLK. Tie
together to receive NRZ data and disable BPV monitor circuitry.
36 RCL O
Receive Carrier Loss. Low-high transition indicates loss of carrier.
37 RBV O
Receive Bipolar Violation. Pulses high during detected bipolar
violations.
38 RFER O
Receive Frame Error. Pulses high when frame alignment, CAS
multiframe alignment or CRC4 words received in error.
39 RLOS O
Receive Loss of Sync. Indicates synchronizer status; high when
frame, CAS and/or CRC4 multiframe search underway, low
otherwise.
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PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
PIN SYMBOL TYPE DESCRIPTION
14
INT
O
Receive Alarm Interrupt. Flags host controller during alarm
conditions. Active low; open drain output.
15 SDI I
Serial Data In. Data for on-chip control registers; sampled on rising
edge of SCLK.
16 SDO O
Serial Data Out. Control and status data from on-chip registers.
Updated on falling edge of SCLK; tri-stated during port write or when
CS is high.
17
CS
I
Chip Select. Must be low to write or read the serial port.
18 SCLK I
Serial Data Clock. Used to write or read the serial port registers.
19 SPS I
Serial Port Select. Tie to V
DD
to select the serial port. Tie to V
SS
to
select the hardware mode.
POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
PIN SYMBOL TYPE DESCRIPTION
20 V
SS
-
Signal Ground. 0.0 volts.
32 TEST I
Test Mode. Tie to V
SS
to select the old DS2181 sync algorithm and to
tri–state the synchronizer status pins on the DS2181AQ. Tie to V
DD
to select the new DS2181A sync algorithm and activate the
synchronizer status pins on the DS2181AQ.
40 V
DD
-
Positive Supply. 5.0 volts.
DS2181A
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REGISTER SUMMARY Table 5
REGISTE
R
ADDRE
SS
T/R
1
DESCRIPTION/FUNCTION
RIMR 0000 R
Receive Interrupt Mask Register. Allows masking of alarm
generated interrupts.
RSR 0001 R
2
Receive Status Register. Reports all receive alarm conditions.
BVCR 0010 R
Bipolar Violation Count Register. 8-bit presettable counter
which records individual bipolar violations.
CECR 0011 R
CRC4 Error Count Register. 8-bit presettable counter which
records individual errors.
FECR 0100 R
Frame Error Count Register. 8-bit presettable counter which
logs individual errors in the received frame alignment signal.
RCR 0101 R
Receive Control Register. Establishes receive side operating
characteristics.
CCR 0110 T/R
Common Control Register. Establishes additional operating
characteristics for transmit and receive sides.
TCR 0111 T
Transmit Control Register. Establishes transmit side operation
characteristics.
TIR1
TIR2
TIR3
TIR4
1000
1001
1010
1011
T Transmit Idle Registers. Designates which outgoing timeslots are
to be substituted with idle code.
TINR 1100 T Transmit International and National Register. When enabled via
the TCR, contents inserted into the outgoing national and/or
international bit positions.
TXR 1101 T Transmit Extra Register. When enabled via the TCR, contents
inserted into the out going extra bit positions.
NOTES:
1. Transmit or receive side register.
2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations must be programmed to 0.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2181A serve as a microprocessor/ microcontroller-compatible serial port.
Fourteen on-chip registers allow the user to update operational characteristics and monitor device status
via a host controller, minimizing hardware interfaces.
Port read/write timing is unrelated to the chip transmit and receive timing, allowing asynchronous reads
and/ or writes by the host. The timing set is identical to that of 8051-type microcontrollers operating in
serial port mode 0. For proper operation of the port and the transmit and receive registers, the user should
provide TCLK and RCLK as well as SCLK.

DS2181AN

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Telecom Interface ICs CEPT Primary Rate Transceiver
Lifecycle:
New from this manufacturer.
Delivery:
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