DS2181A
3 of 32
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PIN SYMBOL TYPE DESCRIPTION
1 TMSYNC I Transmit Multiframe Sync. Low-high transition establishes start of
CAS and/or CRC4 multiframe. Can be tied low, allowing internal
multiframe counter to run free.
2 TFSYNC I Transmit Frame Sync. Low-high transition every frame period
establishes frame boundaries. Can be tied low, allowing TMSYNC to
establish frame boundaries.
3TCLK ITransmit Clock. 2.048 MHz primary clock.
4TCHCLK O Transmit Channel Clock. 256 kHz clock which identifies timeslot
boundaries. Useful for parallel-to-serial conversion of channel data.
5TSER ITransmit Serial Data. NRZ data input, sampled on falling edges of
TCLK.
6TMO OTransmit Multiframe Out. Output of multiframe counter; high
during frame 0, low otherwise.
7TXD ITransmit Extra Data. Sampled on falling edge of TCLK during bit
times 5, 7, and 8 of timeslot 16 in frame 0 when CAS signaling is
enabled.
8TSTS OTransmit Signaling Timeslot. High during timeslot 16 of every
frame, low otherwise.
9TSD ITransmit Signaling Data. CAS signaling data input; sampled on
falling edges of TCLK for insertion into outgoing timeslot 16 when
enabled.
10 TIND I Transmit International and National Data. Sampled on falling
edge of TCLK during bit 1 time of timeslot 0 every frame
(international) and/or during bit times 4 through 8 of timeslot 0 during
non-align frames (national) when enabled.
11 TAF O Transmit Alignment Frame. High during frames containing the
frame alignment signal, low otherwise.
12
13
TPOS
TNEG
O Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
SYCHRONIZER STATUS PIN (44-PIN PLCC ONLY) Table 2A
PIN SYMBOL TYPE DESCRIPTION
3RMSA OReceive Multiframe Search Active. This pin will transition high
when the synchronizer searching for the CAS multiframe alignment
word is active.
6RFSA OReceive Frame Search Active. This pin will transition high when the
synchronizer searching for the FAS is active.
25 RCTO O Receive CRC4 Time Out. This pin will transition high when the
RCTO counter reaches its maximum count of 32. The pin will return
low when either the DS2181AQ reaches CRC4 multiframe
synchronization, or if CRC4 is disabled via CRC.2, or if the device is
issued a hardware reset via the RST pin.
28 RCSA O Receive CRC4 Search Active. This pin will transition high when the
synchronizer searching for the CRC4 multiframe alignment word is
active.
