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RESET
A high-low transition on RST clears all internal registers except the three error counters; a resync is
initiated until RST returns high. RST must be held low on system power-up and when switching to/from
the hardware mode. Following reset, the host processor should update all on-chip registers to establish
desired operating modes.
HARDWARE MODE
An on-chip hardware control mode simplifies preliminary system prototyping and serves applications
which do not require the features of the serial port. Tying SPS low disables the serial port, clears all
internal register locations except those shown below, and redefines pins 14 through 18 as mode control
inputs. The mode control inputs establish device operational characteristics as shown in Table 8. The
hardware mode simplifies device retrofit into existing applications where control interfaces are designed
with discrete logic.
HARDWARE MODE CONTROL Table 8
PIN NUMBER REGISTER LOCATION NAME AND DESCRIPTION
14
(16)
TINR.5
TRA - Transmit Remote Alarm
0 = Normal operation
1 = Enable alarm
15
(17)
TXR.2
TDMA - Transmit Distant Multiframe
Alarm
0 = Normal operation
1 = Enable alarm
16
(18)
CCR.5/CCR.4
Data Format
0 = Input and output data AMI coded
1 = Input and output data HDB3 coded
17
(19)
CCR.3/CCR.2
Transmit and Receive CRC4 Multiframe
0 = Disabled
1 = Enabled
18
(20)
TCR.5/RCR.5
Transmit and Receive CAS Multiframe
0 = Enabled
1 = Disabled
NOTE:
1. Pin numbers for PLCC package are listed in parenthesis.
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -1.0V to +7.0V
Operating Temperature 0° to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Logic 1 V
IH
2.0 V
DD
+.3 V
Input Logic 0 V
IL
-0.3 +0.8 V
Supply V
DD
4.5 5.5 V
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; V
DD
= 5.0V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Current I
DD
6 10 mA 1,2
Input Leakage I
IL
-1.0 +1.0 µA 3
Output Current @ 2.4V I
OH
-1.0 mA 4
Output Current @ .4V I
OL
+4.0 mA 5
Output Leakage I
LO
-1.0 +1.0 µA 6
NOTES:
1. TCLK = RCLK = 2.048 MHz.
2. Outputs open.
3. 0V < V
IN
< V
DD
.
4. All outputs except INT , which is open collector.
5. All outputs.
6. Applies to SDO when tri-stated.
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SERIAL PORT WRITE AC TIMING DIAGRAM Figure 28
NOTE:
1. Shaded regions indicate “don’t care” states of input data.
SERIAL PORT READ
1
AC TIMING Figure 29
NOTE:
1. Serial port write must precede a port read to provide address information.

DS2181AQN+

Mfr. #:
Manufacturer:
Description:
IC TXRX CEPT PRIMARY RATE 44PLCC
Lifecycle:
New from this manufacturer.
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