NCP81038MNTWG

© Semiconductor Components Industries, LLC, 2013
October, 2013 Rev. 10
1 Publication Order Number:
NCP81038/D
NCP81038
Synchronous Buck Controller
with Auto Power Saving
Mode and Built-In LDO
NCP81038 is a dual synchronous buck controller that is optimized
for converting the battery voltage or adaptor voltage into multiple
power rails required in desktop and notebook system. NCP81038
consists of two buck switching controllers with fixed 5.0 V output on
channel 2, 3.3 V on channel 1 and two onboard LDOs with three
outputs: 5 V / 60 mA and 3.3 V or 12 V / 10 mA. NCP81038 supports
high efficiency, fast transient response and provides power good
signals. ON Semiconductor proprietary adaptiveripple control
enables seamless transition from CCM to DCM, where converter runs
at reduced switching frequency with much higher efficiency at light
load. The part operates with supply voltage ranging from 5.5 V to
28 V. NCP81038 is available in a 28pin QFN package.
Features
Wide Input Voltage Range: from 5.5 V to 28 V
Builtin 5 V / 60 mA LDO
Builtin selectable 3.3 V or 12 V / 10 mA LDO
Three Selectable Fixed Frequency 300 KHz, 400 KHz or 600 KHz
180 Interleaved Operation Between the Two Channels in
ContinueConductionMode (CCM)
Selected PowerSaving Mode/Forced PWM Mode
TransientResponseEnhancement (TRE) Control
Input Supply Voltage Feed Forward Control
Resistive or Lossless Inductors DCR Current Sensing
OverTemperature Protection
Internal Fixed 8.5 ms SoftStart
Fixed Output Voltages 5 V and 3.3 V
Power Good Outputs for Both Channels
Builtin Adaptive Gate Drivers
Output Discharge Operation
Builtin OverVoltage, UnderVoltage Protection
Accurate OverCurrent Protection
Thermal Shutdown
Applications
Desktop / Notebook Computers
System Power Supplies
I/O Power Supplies
28 PIN QFN, 4x4
MN SUFFIX
CASE 485AR
Device Package Shipping
ORDERING INFORMATION
NCP81038MNTWG QFN28
(PbFree)
4,000 /
Tape & Reel
MARKING
DIAGRAM
81038 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
http://onsemi.com
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
PIN CONNECTIONS
(Top View)
(Note: Microdot may be in either location)
81038
ALYWG
G
1
GH1
BST1
SWN1
GL1/FSET
PGND1
CSP1
CSN1
GH2
BST2
SWN2
GL2
PGND2
CSP2
CSN2
FB2
COMP2
EN2/SS2
PG
EN1/SS1
COMP1
FB1
5V_LDOBYP
5V_LDOOUT
5V_LDOEN
SKIP
LDO2_EN
LDO2_OUT
VIN
GND
1
28
NCP81038
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2
Figure 1. Block Diagram
+
ENABLE
LDO2_EN
+
CSP1
CSN1
CSA
LDO2_OUT
GH1
GL1/
BST1
PGND1
SW1
+
E/A
COMP1
FB1
VREF
SS
OC & TRE Detection
EN1
PG
GND
SKIP
VIN
+
+
ENABLE
LDO
VREF
5V_LDOEN
VIN
5V_LDOOUT
Switcher 1 Shown
Vbias
Vbias
5V_LDOBYP
PG1
PG2
5V_LDOOUT
FSET
Control Logic
Ramp Generator
And
PWM Logic
UVLO,
UVP, OVP,
Power Good
OCP, TSD and
Protection
NCP81038
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3
Table 1. PIN DESCRIPTIONS
Pin
No.
Symbol Description
1, 21 GH1, GH2 Gate driver output of the top Nchannel MOSFET.
2, 20 BST1, BST2 Top gate driver input supply, a bootstrap capacitor connection between SWNx and this pin.
3, 19 SWN1, SWN2 Switch node between the top MOSFET and bottom MOSFET.
4 GL2 Gate driver output of bottom Nchannel MOSFET in channel2.
18 GL1/FSET Gate driver output of bottom Nchannel MOSFET in channel1. And it is also used to set up switching
frequency by connecting a resistor from this pin to ground.
5, 17 PGND1, PGND2 Power ground for channel 1 & 2.
6, 16 CSP1, CSP2 Inductor current differential sense noninverting input.
7, 15 CSN1, CSN2 Inductor current differential sense inverting input.
8, 14 FB1, FB2 Output voltage feed back.
9, 13 COMP1, COMP2 Output of the error amplifier.
10, 12 EN1, EN2 Channel 1 and channel 2 enable pin. Short this pin to ground to disable the switcher channel. Pull this
pin high to enable the switcher channel.
11 PG Power good indicator for both output voltages. Opendrain output.
22 VIN Battery or Adaptor input voltage
23 LDO2_OUT
Second internal LDO output. A capacitor of minimum 1.0 mF is recommended to connect between this
pin and ground.
24 LDO2_EN Enable for second internal LDO
Tie to VCC to setup LDO2 output at 12 V
Tie to 1/2VCC to setup LDO2 output at 3.3 V
Tie to ground to disable LDO
25 SKIP DCM programming pin:
Ground this pin to setup automatic CCMDCM transfer with 33 KHz minimum switching
frequency limitation;
Connect this pin to VCC to force CCM operation;
Leave this pin open to give automatic CCMDCM transfer with 33 KHz minimum switching
frequency for channel 1 but forced CCM for channel 2.
26 5V_LDOEN Enable for internal 5 V LDO.
27 5V_LDOOUT
The output for internal 5 V LDO. A capacitor of minimum 4.7 mF is recommended to connect between
this pin and ground.
28 5V_LDOBYP 5 V LDO bypass pin.
EPad GND.

NCP81038MNTWG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers SYNCHRONOUS BUCK CONTROLL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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