NCP81038
http://onsemi.com
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DETAILED DESCRIPTION
Overview
The NCP81038 is a cost effective dual output controllers
with three selectable LDO outputs suitable for desktop and
server application. It provides one independent LDO which
is 5 V/100 mA, two selectable LDOs which is 12 V or
3.3 V/10 mA, and two synchronous PWM controllers that
incorporate all the control and protection circuitry necessary
to satisfy a wide range of applications. The NCP81038
PWM switchers employ adaptive−ripple control to provide
seamless transition between CCM and DCM while maintain
high efficiency during light load. It also provides fast
transient response and excellent stability. The features of the
NCP81038 include a precision reference, selectable
switching frequency, an error amplifier, adaptive gate
driver, programmable soft−start, and very low shutdown
current. The protection features of the NCP81038 include
fixed/programmable soft−start, over−current protection,
wide input voltage range, power good monitor, over voltage
and under voltage protection, built in output discharge and
thermal shutdown.
5V LDO and Switchover (5V_LDOOUT)
The NCP81038 includes a high−current (100 mA) linear
regulator that is configured for 5 V operation, which is bias
supply necessary to power up the main analog supply rail for
the IC and provides the current for the gate drivers. When the
3.3 V switching regulator is running and the 5 V switching
regulator is still off (EN2 = 0), the 5 V linear regulator can
provide about 80 mA to external load, while the remaining
20 mA is consumed by the 3.3 V regulator’s MOSFETS’
switching, giving typical switching frequency and
MOSFETS’ gate capaciatance. Once the 5 V switching
regulator is enabled, this 5V_LDO may be bypassed using
5V_LDOBYP input. Typically, a capacitor with 10−mF or
higher is needed to keep 5V_LDO stable. Additionally, if
VOUT2 voltage exceeds 4.75 V, the 5V_LDO is switched
off and VOUT2 (5V buck output) is connected to
5V_LDOOUT through a bypass FET (typical 1 ohm) to
provide 5 V rail. With this bypass function, the whole system
efficiency is improving. The 5V_LDOEN pin is high
voltage and can be connected to VIN voltage. However,
5V_LDOEN is not allowed to go beyond VIN pin voltage.
LDO2_OUT
The NCP81038 includes 10 mA linear regulators that can
be programmed for 12 V or 3.3 V operations. LDO2 can be
enabled only when VCC is present. When LDO2_EN is
connected to VCC, LDO2_OUT is programmed at 12 V.
When LDO2_EN is connected to 1/2VCC, LDO2_OUT is
set at 3.3 V. Typically, a minimum capacitor with 1.0−mF or
higher is needed to keep LDO2_OUT stable.
Reference Voltage
The NCP81038 incorporates an internal reference that
allows output voltages as low as 0.8 V. The tolerance of the
internal reference is guaranteed over the entire operating
temperature range of the controller. The reference voltage is
trimmed using a test configuration that accounts for error
amplifier offset and bias currents.
Oscillator Frequency
A fixed precision oscillator is provided. The actual
switching frequency is set at 300 KHz, 400 KHz or 600 KHz
by the resistor on GL1/FSET pin. The resistor and frequency
can be referred to the table below.
FSET resistor 1.8 K 9.1 K 16 K
Switching Frequency 300 KHz 400 KHz 600 KHz
Error Amplifier
The error amplifier’s primary function is to regulate the
converter’s output voltage using a resistor divider connected
from the converter’s output to the FB pin of the controller,
as shown in the Applications Schematic. A type III
compensation network must be connected around the error
amplifier to stabilize the converter. It has a bandwidth of
greater than 15 MHz, with open loop gain of at least 80 dB.
The COMP output voltage is clamped to a level above the
oscillator ramp in order to improve large−scale transient
response.
Soft−Start
To limit the start−up inrush current, an internal soft start
circuit is used to ramp up the reference voltage from 0 V to
its final value linearly. The internal soft start time is 13 ms
typically, from EN assertion to Vout ready. It includes a
delay of 240 ms from EN assertion to the Vout ramp starting.
500 ms after both channel Vout ready, the PG (Power Good)
is asserted.
Soft−Stop
Soft−Stop or discharge mode is always on during faults or
disable. In this mode, a fault (UVP, OCP, TSD) or disable
(EN) causes the output to be discharged through an internal
20−ohm transistor inside of VO terminal. The time constant
of soft−stop is a function of output capacitance and the
resistance of the discharge transistor.
Adaptive Non−Overlap Gate Driver
In a synchronous buck converter, a certain dead time is
required between the low side drive signal and high side
drive signal to avoid shoot through. During the dead time,
the body diode of the low side FET free-wheels the current.
The body diode has much higher voltage drop than that of
the MOSFET, which reduces the efficiency significantly.
The longer the body diode conducts, the lower the
efficiency. NCP81038 implements adaptive dead time
control to minimize the dead time, as well as preventing
shoot through from happening.
