NCP4201
http://onsemi.com
12
Figure 8 shows typical startup waveforms for the
NCP4201.
Figure 8. Typical Startup Waveforms
Phase Detection
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the NCP4201
operates as a 4−phase PWM controller.
To operate as a 3−Phase Controller: connect PWM4 to V
CC
.
To operate as a 2−Phase Controller: connect PWM3 and
PWM4 to V
CC
.
To operate as a single phase controller: connect PMW2,
PWM3, and PWM4 to V
CC
.
Prior to soft−start, while EN is high the PWM4, PWM3
and PWM2 pins sink approximately 100 mA each. An
internal comparator checks each pin’s voltage vs. a threshold
of 3.0 V. If the pin is tied to V
CC
, it is above the threshold.
Otherwise, an internal current sink pulls the pin to GND,
which is below the threshold. PWM1 is low during the phase
detection interval that occurs during the first six clock cycles
of TD2. After this time, if the remaining PWM outputs are
not pulled to V
CC
, the 100 mA current sink is removed, and
they function as normal PWM outputs. If they are pulled to
V
CC
, the 100 mA current source is removed, and the outputs
are put into a high impedance state.
The PWM outputs are logic−level devices intended for
driving fast response external gate drivers such as the
ADP3121. Because each phase is monitored independently,
operation approaching 100% duty cycle is possible. In
addition, more than one output can be on at the same time to
allow overlapping phases.
Master Clock Frequency
The clock frequency of the NCP4201 is set with an
external resistor connected from the RT pin to ground. The
frequency follows the graph in Figure 3. To determine the
frequency per phase, the clock is divided by the number of
phases in use. If all phases are in use, divide by 4. If 2 phases
are in use then divide by 2.
Output Voltage Differential Sensing
The NCP4201 combines differential sensing with a high
accuracy VID DAC and reference, and a low offset error
amplifier. This maintains a worst−case specification of
±9 mV differential sensing error over its full operating
output voltage and temperature range. The output voltage is
sensed between the FB pin and FBRTN pin. FB is connected
through a resistor, R
B
, to the regulation point, usually the
remote sense pin of the microprocessor. FBRTN is
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a minimal current of 70 mA to allow
accurate remote sensing. The internal error amplifier
compares the output of the DAC to the FB pin to regulate the
output voltage.
Output Current Sensing
The NCP4201 provides a dedicated Current Sense
Amplifier (CSA) to monitor the total output current for
proper voltage positioning vs. load current, for the I
MON
output and for current limit detection. Sensing the load
current at the output gives the total real time current being
delivered to the load, which is an inherently more accurate
method than peak current detection or sampling the current
across a sense element such as the low−side MOSFET. This
amplifier can be configured in several ways, depending on
the objectives of the system, as follows:
• Output inductor DCR sensing without a thermistor for
lower cost.
• Output inductor DCR sensing with a thermistor for
improved accuracy with inductor temperature tracking.
• Sense resistors for highest accuracy measurements.
The positive input of the CSA is connected to the CSREF
pin, which is connected to the average output voltage. The
inputs to the amplifier are summed together through
resistors from the sensing element, such as the switch node
side of the output inductors, to the inverting input CSSUM.
The feedback resistor between CSCOMP and CSSUM sets
the gain of the amplifier and a filter capacitor is placed in
parallel with this resistor. The gain of the amplifier is
programmable by adjusting the feedback resistor. This
difference signal is used internally to offset the VID DAC
for voltage positioning. This difference signal can be
adjusted between 50% and 150% of the external value using
the PMBus Load−line Calibration (0xDE) and Load−line
Set (0xDF) commands. The difference between CSREF and
CSCOMP is used as a differential input for the current limit
comparator.
To provide the best accuracy for sensing current, the CSA
is designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors to make it
extremely accurate.
