NCP4201MNR2G Datasheet NCP4201MNR2G | P13-P15

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The CPU current can also be monitored over the PMBus.

The current limit and the load−line can be adjusted from the

circuit component values over the PMBus.

Current Limit Set−Point

The current limit threshold on the NCP4201 is

programmed by a resistor between the I

LIMFS

pin and the

CSCOMP pin. The I

LIMFS

current, I

ILIMFS

, is compared

with an internal current reference of 20 mA. If I

ILIMFS

exceeds 20 mA then the output current has exceeded the limit

and the current limit protection is tripped.

ILIMFS

* V

CSCOMP

ILIMFS

(eq. 1)

Where V

ILIMFS

= V

CSREF

* V

CSCOMP

LOAD

(eq. 2)

ILIMFS

CSREF

* V

CSCOMP

ILIMFS

Assuming that:

+ 1mW

(eq. 3)

i.e. the external circuit is set up for a 1 mW load−line then

the R

ILIMFS

is calculated as follows:

ILIMFS

1mW I

LOAD

ILIMITFS

(eq. 4)

Assuming we want a current limit of 150 A that means that

LIMFS

must equal 20 mA at that load.

20 mA +

1mW 150 A

ILIMITFS

+ 7.5 kW

(eq. 5)

Solving this equation for R

LIMITFS

we get 7.5 kW.

The current limit threshold can be modified from the

resistor programmed value by using the PMBus interface

using Bits <4:0> of the Current Limit Threshold command

(0xE2). The limit is programmable between 50% of the

external limit and 146.7% of the external limit. The

resolution is 3.3%. Table 3 gives some examples codes.

Table 3. Current Limit

Code Current Limit (% of External Limit)

0 0000 50%

0 0001 53.3%

1 0000 100% = default

1 0001 103.3%

1 1110 143.3%

1 1111 146.7%

Current Limit, Short−Circuit and Latchoff Protection

If the current limit is reached and TD5 has completed, an

internal latchoff delay time will start, and the controller will

shut down if the fault is not removed. This delay is four times

longer than the delay time during the startup sequence. The

current limit delay time only starts after TD5 has completed.

If there is a current limit during startup, the NCP4201 will

go through TD1 to TD5 and then start the latchoff time.

Because the controller continues to cycle the phases during

the latchoff delay time, if the short is removed before the

timer is complete, the controller can return to normal

operation.

The latchoff function can be reset by either removing/

reapplying the supply voltage to the NCP4201, or by

toggling the EN pin low for a short time.

During startup when the output voltage is below 200 mV,

a secondary current limit is active. This is necessary because

the voltage swing of CSCOMP cannot go below ground.

This secondary current limit limits the internal COMP

voltage to the PWM comparators to 1.5 V. This limits the

voltage drop across the low−side MOSFETs through the

current balance circuitry. Typical overcurrent latchoff

waveforms are shown in Figure 9.

Figure 9. Overcurrent Latchoff Waveforms

An inherent per phase current limit protects individual

phases if one or more phases stop functioning because of a

faulty component. This limit is based on the maximum

normal mode COMP voltage.

Output Current Monitor

MON

is an analog output from the NCP4201 representing

the total current being delivered to the load. It outputs an

accurate current that is directly proportional to the current

set by the I

LIMFS

resistor.

IMON

+ 10 I

ILIMFS

(eq. 6)

The current is then run through a parallel RC connected

from the I

MON

pin to the FBRTN pin to generate an

accurately scaled and filtered voltage as per the

specification. The size of the resistor is used to set the I

MON

scaling.

The scaling is set such that I

MON

= 900 mV at the TDC

current of the processor. This means that the R

IMON

resistor

should be chosen as follows.

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From the Current Limit Set−point paragraph we know the

following:

ILIMFS

1mW I

LOAD

LIMIFS

(eq. 7)

IMON

+ 10

1mW I

LOAD

LIMFS

For a 150 A current limit R

LIMFS

= 7.5 kW. Assuming the

TDC = 135 A then V

MON

should equal 900 mV when

LOAD

= 135 A.

When I

LOAD

= 135 A, I

MON

equals:

(eq. 8)

IMON

+ 10

1mW 135 A

7.5 kW

+ 180 mA

IMON

+ 900 mV + 180 mA R

MON

This gives a value of 5 kW for R

MON

If the TDC and OCP limit for the processor have to be

changed the because the I

LIMITFS

resistor sets up both the

current limit and also the current out of the I

MON

pin, as

explained earlier.

The I

MON

pin also includes an active clamp to limit the

MON

voltage to 1.15 V MAX while maintaining accuracy

at 900 mV full scale.

Active Impedance Control Mode

For controlling the dynamic output voltage droop as a

function of output current, the CSA gain and load−line

programming can be scaled to be equal to the droop

impedance of the regulator times the output current. This

droop voltage is then used to set the input control voltage to

the system. The droop voltage is subtracted from the DAC

reference input voltage directly to tell the error amplifier

where the output voltage should be. This allows enhanced

feed forward response.

Load−Line Setting

The load−line is programmable over the PMBus on the

NCP4201. It is programmed using the Load−line

Calibration (0xDE) and Load−line Set (0xDF) commands.

The load−line can be adjusted between 0% and 100% of the

external R

CSA

. In this example R

CSA

= 1 mW R

needs to

0.8 mW therefore programming the Load−line Calibration +

Load−line Set register to give a combined percentage of

80% will set the R

to 0.8 mW

Table 4. Load−line Commands

Code Load−line (as a percentage of R

CSA

)

0 0000 0%

0 0001 3.226%

1 0000 51.6% = default

1 0001 53.3%

1 1110 96.7%

1 1111 100%

Current Control Mode and Thermal Balance

The NCP4201 has individual inputs (SW1 to SW4) for

each phase that are used for monitoring the per phase

current. This information is combined with an internal ramp

to create a current balancing feedback system that has been

optimized for initial current balance accuracy and dynamic

thermal balancing during operation. This current balance

information is independent of the average output current

information used for positioning. The magnitude of the

internal ramp can be set to optimize the transient response

of the system. It also monitors the supply voltage for

feed−forward control for changes in the supply. A resistor

connected from the power input voltage to the RAMPADJ

pin determines the slope of the internal PWM ramp.

The balance between the phases can be programmed using

the PMBus Phase Bal SW(x) commands (0xE3 to 0xE6).

This allows each phase to be adjusted if there is a difference

in temperature due to layout and airflow considerations. The

phase balance can be adjusted from a default gain of 5 (Bits

4:0 = 10000). The minimum gain programmable is 3.75

(Bits 4:0 = 00000) and the max gain is 6.1718 (Bits 4:0 =

11111).

Voltage Control Mode

A high gain, high bandwidth, voltage mode error

amplifier is used for the voltage mode control loop. The

control input voltage to the positive input is set via the VID

logic according to the voltages listed in Table 10. The VID

code is set using the VID Input pins or it can be programmed

over the PMBus using the VOUT_Command. By default,

the NCP4201 outputs a voltage corresponding to the VID

Inputs. To output a voltage following the VOUT_Command

the user first needs to program the required VID Code. Then

the VID_EN Bits need to be enabled. The following is the

sequence:

1. Program the required VID Code to the

VOUT_Command code (0x21).

2. Set the VID_EN bit (Bit 3) in the VR Config 1 A

(0xD2) and on the VR Config 1B (0xD3).

This voltage is also offset by the droop voltage for

active positioning of the output voltage as a

function of current, commonly known as active

voltage positioning. The output of the amplifier is

the COMP pin, which sets the termination voltage

for the internal PWM ramps.

The negative input (FB) is tied to the output sense

location with Resistor R

and is used for sensing

and controlling the output voltage at this point. A

current source (equal to IREF) from the FB pin

flowing through R

is used for setting the no load

offset voltage from the VID voltage. The no load

voltage is negative with respect to the VID DAC

for Intel CPU’s.

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The value of R

can be found using the following

equation:

VID

* V

ONL

(eq. 9)

An offset voltage can be added to the control voltage over

the serial interface. This is done using Bits <5:0> of the

VOUT_TRIM (0xDB) and VOUT_CAL (0xDC)

Commands. The max offset that can be applied is

±193.75 mV (even if the sum of the offsets > 193.75 mV).

The LSB size is 6.25 mV. A positive offset is applied when

Bit 5 = 0. A negative offset is applied when Bit 5 = 1.

Table 5. Offset Codes

VOUT_

TRIM

CODE

TRIM

OFFSET

VOLTAGE

VOUT_

CAL

CODE

CAL

OFFSET

VOLTAGE

TOTAL

OFFSET

VOLTAGE

00 1000 50 mV 00 0010 12.5 mV 62.5 mV

10 0001 −6.25 mV 10 1110 −87.5 mV −93.75 mV

00 1111 93.75 mV 10 0001 −6.25 mV 87.5 mV

Dynamic VID

The NCP4201 has the ability to respond to dynamically

changing VID inputs while the controller is running. This

allows the output voltage to change while the supply is

running and supplying current to the load. This is commonly

referred to as Dynamic VID (DVID). A DVID can occur

under either light or heavy load conditions. The processor

signals the controller by changing the VID inputs (or by

programming a new VOUT_Command) in a single or

multiple steps from the start code to the finish code. This

change can be positive or negative.

When a VID bit changes state, the NCP4201 detects the

change and ignores the DAC inputs for a minimum of 200

ns. This time prevents a false code due to logic skew while

the VID inputs are changing. Additionally, the first VID

change initiates the PWRGD and CROWBAR blanking

functions for a minimum of 100 ms to prevent a false

PWRGD or CROWBAR event. Each VID change resets the

internal timer.

If a VID off code is detected the NCP4201 will wait for

5 msec to ensure that the code is correct before initiating a

shutdown of the controller.

The NCP4201 also uses the TON_Transition command

code (0xD6) to limit the DVID slew rates. These can be

encountered when the system does a large single VID step

for power state changes, thus the DVID slew rate needs to

be limited to prevent large inrush currents.

The transition slew rate is programmed using Bits <2:0>

of the Ton_Transition (0xD6) command code. Table 6

provides the soft−start values.

Table 6. Transition Rate Codes

Code Transition Rate (V/msec)

000 1

001 3

010 5 = default

011 7

100 9

101 11

110 13

111 15

Enhanced Transients Mode

The NCP4201 incorporates enhanced transient response

for both load step up and load release. For load step up it

senses the output of the error amp to determine if a load step

up has occurred and then sequences on the appropriate

number of phases to ramp up the output current.

For load release, it also senses the output of the error amp

and uses the load release information to trigger the TRDET

pin, which is then used to adjust the error amp feedback for

optimal positioning. This is especially important during

high frequency load steps.

Additional information is used during load transients to

ensure proper sequencing and balancing of phases during

high frequency load steps as well as minimizing the stress on

components such as the input filter and MOSFETs.

Reference Current

The I

REF

pin is used to set an internal current reference.

This reference current sets I

. A resistor to ground

programs the current based on the 1.8 V output.

REF

1.8 V

IREF

(eq. 10)

Typically, R

IREF

is set to 121 kW to program I

REF

= 15 mA.

(eq. 11)

+ I

REF

+ 15 mA

Power Good Monitoring

The power good comparator monitors the output voltage

via the CSREF pin. The PWRGD pin is an open−drain

output whose high level (when connected to a pullup

resistor) indicates that the output voltage is within the

nominal limits. The nominal limits specified in the

specifications above based on the VID voltage setting.

PWRGD goes low if the output voltage is outside of this

specified range, if the VID DAC inputs are in no CPU mode,

or whenever the EN pin is pulled low. PWRGD is blanked

during a DVID event for a period of 100 ms to prevent false

signals during the time the output is changing.

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NCP4201MNR2G

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