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ICS9FG104DGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
IDT
®
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C—12/16/10
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
10
SMBus Table: Reserved Register
Pin # Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: Reserved Register
Pin # Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: M/N Programming Enable
Pin # Name Control Function Type 0 1 Default
Bit 7
M/N_Enable M/N Prog. Enable RW Disable Enable 0
Bit 6
1
Bit 5
REFOUT_En REFOUT Enable RW Disable Enable 1
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: PLL Frequency Control Register
Pin # Name Control Function Type 0 1 Default
Bit 7
PLL N Div8 N Divider Prog bit 8 RW X
Bit 6
PLL N Div9 N Divider Prog bit 9 RW X
Bit 5
PLL M Div5 RW X
Bit 4
PLL M Div4 RW X
Bit 3
PLL M Div3 RW X
Bit 2
PLL M Div2 RW X
Bit 1
PLL M Div1 RW X
Bit 0
PLL M Div0 RW X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
Reserved
Reserved
Reserved
-
-
-
-
Byte 7
-
-
-
-
-
-
-
Byte 8
-
-
-
Reserved
Reserved
Reserved
Reserved
5
- Reserved
Reserved
Byte 9
-
-
- Reserved
Reserved
Reserved
Reserved
- Reserved
-
-
-
Byte 10
-
The decimal representation of M
and N Divider in Byte 11 and 12 will
configure the PLL VCO frequency.
Default at power up = latch-in or
Byte 0 Rom table. VCO Frequency
= fXTAL x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
-
M Divider Programming
bit (5:0)
-
-
-
-
-
IDT
®
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C—12/16/10
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
11
SMBus Table: PLL Frequency Control Register
Pin # Name Control Function Type 0 1 Default
Bit 7
PLL N Div7 RW X
Bit 6
PLL N Div6 RW X
Bit 5
PLL N Div5 RW X
Bit 4
PLL N Div4 RW X
Bit 3
PLL N Div3 RW X
Bit 2
PLL N Div2 RW X
Bit 1
PLL N Div1 RW X
Bit 0
PLL N Div0 RW X
SMBus Table: PLL Spread Spectrum Control Register
Pin # Name Control Function Type 0 1 Default
Bit 7
PLL SSP7 RW X
Bit 6
PLL SSP6 RW X
Bit 5
PLL SSP5 RW X
Bit 4
PLL SSP4 RW X
Bit 3
PLL SSP3 RW X
Bit 2
PLL SSP2 RW X
Bit 1
PLL SSP1 RW X
Bit 0
PLL SSP0 RW X
SMBus Table: PLL Spread Spectrum Control Register
Pin # Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
PLL SSP14 RW X
Bit 5
PLL SSP13 RW X
Bit 4
PLL SSP12 RW X
Bit 3
PLL SSP11 RW X
Bit 2
PLL SSP10 RW X
Bit 1
PLL SSP9 RW X
Bit 0
PLL SSP8 RW X
Byte 11
-
N Divider Programming
Byte11 bit(7:0) and Byte10
bit(7:6)
The decimal representation of M
and N Divider in Byte 11 and 12 will
configure the PLL VCO frequency.
Default at power up = latch-in or
Byte 0 Rom table. VCO Frequency
= fXTAL x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
-
-
-
-
-
-
Byte 12
-
Spread Spectrum
Programming bit(7:0)
These Spread Spectrum bits in
Byte 13 and 14 will program the
spread pecentage of PLL
-
-
-
-
-
-
-
Byte 13
- Reserved
Spread Spectrum
Programming bit(14:8)
These Spread Spectrum bits in
Byte 13 and 14 will program the
spread pecentage of PLL
-
-
-
-
-
-
-
IDT
®
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C—12/16/10
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
12
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP# - Assertion (transition from '1' to '0')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
DIF_STOP# - De-assertion (transition from '0' to '1')
DIF_STOP#
DIF
DIF#
DIF_Stop#
Tdrive_DIF_Stop, 15nS >200mV
DIF
DIF#
DIF Internal
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ICS9FG104DGLF

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Description:
IC FREQ TIMING GENERATOR 28TSSOP
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