ICS9FG104DGLF Datasheet ICS9FG104DFLFT, ICS9FG104DGILFT, ICS9FG104DGLF | P7-P9

IDT

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C—12/16/10

ICS9FG104D

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

General SMBus serial interface information for the ICS9FG104D

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address DC

(H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

• ICS clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address DC

(h)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address DD

(h)

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

Byte N + X -1

• ICS clock sends

Byte 0 through byte X (if X

(h)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Slave/Receiver)

ACK

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

stoP bit

X Byte

Index Block Write Operation

Slave Address DC

(h)

Beginning Byte = N

WRite

starT bit

Controller (Host)

TstarT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

Slave Address DD

(h)

Index Block Read Operation

Slave Address DC

(h)

Beginning Byte = N

ACK

Data Byte Count = X

ACK

ICS (Slave/Receiver)

Controller (Host)

X Byte

ACK

IDT

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C—12/16/10

ICS9FG104D

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)

Pin # Name Control Function Type 0 1 Default

Bit 7

RW Pin 17

Bit 6

RW Pin 6

Bit 5

RW Pin 24

Bit 4

RW Pin 25

Bit 3

RW Off On Pin 16

Bit 2

RW Hardware Select Software Select 0

Bit 1

RW Driven Hi-Z 0

Bit 0

RW Down Center 0

Notes:

1. These bits reflect the state of the corresponding pins at power up, but may be written to

if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.

SMBus Table: Output Enable Register

Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

DIF_3 EN Output Enable RW Disable Enable 1

Bit 5

DIF_2 EN Output Enable RW Disable Enable 1

Bit 4

Bit 3

Bit 2

DIF_1 EN Output Enable RW Disable Enable 1

Bit 1

DIF_0 EN Output Enable RW Disable Enable 1

Bit 0

SMBus Table: Output Stop Control Register

Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

DIF_3 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 5

DIF_2 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 4

Bit 3

Bit 2

DIF_1 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 1

DIF_0 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 0

Reserved

See Frequency Selection Table,

Page 1

FS3

FS2

FS1

FS0

Byte 2

Byte 1

DIF_STOP# drive mode

SPREAD TYPE

16 Spread Enable

Enable Software Control of Frequency, Spread Enable

(Spread Type always Software Control)

Byte 0

Reserved

IDT

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C—12/16/10

ICS9FG104D

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

SMBus Table: Frequency Select Readback Register

Pin # Name Control Function Type 0 1 Default

Bit 7

SEL14M_25M#

(FS3)

State of pin 17 R Pin 17

Bit 6

FS2

State of pin 6 R Pin 6

Bit 5

FS1

State of pin 24 R Pin 24

Bit 4

FS0

State of pin 25 R Pin 25

Bit 3

SPREAD

State of pin 26 R Off On Pin 16

Bit 2

Bit 1

Bit 0

Notes:

1. These bits reflect the state of the corresponding pins, regardless of whether software

programming is enabled or not.

SMBus Table: Vendor & Revision ID Register

Pin # Name Control Function Type 0 1 Default

Bit 7

RID3 R - - X

Bit 6

RID2 R - - X

Bit 5

RID1 R - - X

Bit 4

RID0 R - - X

Bit 3

VID3 R - - 0

Bit 2

VID2 R - - 0

Bit 1

VID1 R - - 0

Bit 0

VID0 R - - 1

SMBus Table: DEVICE ID

Pin # Name Control Function Type 0 1 Default

Bit 7

DID7 R - - 0

Bit 6

DID6 R - - 0

Bit 5

DID5 R - - 0

Bit 4

DID4 R - - 0

Bit 3

DID3 R - - 1

Bit 2

DID2 R - - 0

Bit 1

DID1 R - - 0

Bit 0

DID0 R - - 0

SMBus Table: Byte Count Register

Pin # Name Control Function Type 0 1 Default

Bit 7

BC7 RW - - 0

Bit 6

BC6 RW - - 0

Bit 5

BC5 RW - - 0

Bit 4

BC4 RW - - 0

Bit 3

BC3 RW - - 0

Bit 2

BC2 RW - - 1

Bit 1

BC1 RW - - 1

Bit 0

BC0 RW - - 1

Byte 6

Writing to this register will

configure how many bytes will

be read back, default is 07

= 7

bytes.

Byte 5

Byte 4

REVISION ID

VENDOR ID

See Frequency Selection Table,

Page 1

Reserved

Device ID = 08 hex

Byte 3

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ICS9FG104DGLF

Mfr. #:

Buy ICS9FG104DGLF

Manufacturer:

Description:

IC FREQ TIMING GENERATOR 28TSSOP

Lifecycle:

New from this manufacturer.

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ICS9FG104DGLF

ICS9FG104DGLF

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