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CBTL05024BSHP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
CBTL05024 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 March 2014 10 of 21
NXP Semiconductors
CBTL05024
High performance MUX/deMUX switch for Thunderbolt applications
B
3dB
3 dB bandwidth differential - 10 - GHz
t
PD
propagation delay between AUXIO and TB - 70 - ps
t
sk(dif)
differential skew time intra-pair - 5 - ps
V
I
input voltage TB+/TB and AUXIO+/AUXIO 0- V
DD
+0.3 V
V
ID
differential input voltage TB+/TB and AUXIO+/AUXIO --1.2 V
Table 11. TB channel of 2 : 1 10G MUX dynamic and static characteristics …continued
Symbol Parameter Conditions Min Typ Max Unit
Table 12. AUX - AUXIO channel of AUX MUX dynamic and static characteristics
Symbol Parameter Conditions Min Typ Max Unit
DDIL differential insertion loss channel is OFF
f=5MHz - 80 - dB
f = 360 MHz - 60 - dB
channel is ON
f=5MHz - 1.1 - dB
f = 360 MHz - 1.2 - dB
DDRL differential return loss f = 5 MHz - 19 - dB
f = 360 MHz - 18 - dB
DDNEXT differential near-end crosstalk adjacent channels are ON
f=5GHz - 18 - dB
f=2.7GHz - 25 - dB
f = 100 MHz - 60 - dB
f=1MHz - 70 - dB
R
on
ON-state resistance V
DD
=3.3V; I
I
=10mA;
V
IC
=0.9V
DD
for AUXIO;
V
IC
=0.1V
DD
for AUXIO+
-1316
B
3dB
3 dB bandwidth differential - 3 - GHz
t
PD
propagation delay between AUX and AUXIO - 70 - ps
t
sk(dif)
differential skew time intra-pair - 5 - ps
V
I
input voltage AUX+/AUX and AUXIO+/AUXIO 0- V
DD
V
V
IC
common-mode input voltage AUX+/AUX and AUXIO+/AUXIO 0- V
DD
V
V
ID
differential input voltage AUX+/AUX and AUXIO+/AUXIO --1.4V
I
LIH
HIGH-level input leakage current AUX+/AUX pins;
V
DD
=max;V
I
=V
DD
--1 A
I
LIL
LOW-level input leakage current AUX+/AUX pins;
V
DD
=max;V
I
=GND
--1 A
CBTL05024 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 March 2014 11 of 21
NXP Semiconductors
CBTL05024
High performance MUX/deMUX switch for Thunderbolt applications
9.3 DP MUX channel characteristics
Table 13. DDC - AUXIO channel of AUX MUX dynamic and static characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
on
ON-state resistance V
DD
=3.3V; I
I
= 10 mA - 35 50
C
in
input capacitance V
DD
=3.3V; V
I
= 3.3 V - 0.2 - pF
t
PD
propagation delay between DDC and AUXIO - 70 - ps
I
LIH
HIGH-level input leakage current DDC_DAT and DDC_CLK pins;
V
DD
=max; V
I
=V
DD
--1.5 A
I
LIL
LOW-level input leakage current DDC_DAT and DDC_CLK pins;
V
DD
=max; V
I
=GND
--1.5 A
Table 14. Channel dynamic and static characteristics
Symbol Parameter Conditions Min Typ Max Unit
DDIL differential insertion loss DP-DPMLO path; channel is OFF
f=2.7GHz - 20 - dB
f = 1.35 GHz - 35 - dB
f = 100 MHz - 50 - dB
DP-DPMLO path; channel is ON
f=2.7GHz - 1.2 - dB
f = 1.35 GHz - 1.1 - dB
f = 100 MHz - 0.8 - dB
il(se)
single-ended insertion loss LS-DPMLO path; channel is OFF;
f=5MHz
- 60 - dB
LS-DPMLO path; channel is ON;
f=5MHz
- 1- dB
DDRL differential return loss DP-DPMLO path
f=2.7GHz - 15 - dB
f = 100 MHz - 20 - dB
rl(se)
single-ended return loss LS-DPMLO path; f = 5 MHz - 18 - dB
DDNEXT differential near-end crosstalk adjacent channels are ON
f=5GHz - 18 - dB
f=2.7GHz - 25 - dB
f = 100 MHz - 60 - dB
f=1MHz - 70 - dB
R
on
ON-state resistance DP-DPMLO path; V
DD
=3.3V; I
I
=5mA - 9 12
LS-DPMLO path; V
DD
=3.3V; I
I
=5mA - 16 22
initial ON-state resistance before
power supply negotiation done;
V
DD
=2.3V;I
I
=5mA
-3550
B
3dB
3 dB bandwidth differential; DP-DPMLO path - 5.5 - GHz
single-ended; LS-DPMLO path - 1 - GHz
t
PD
propagation delay between DP+/DP and
DPMLO+/DPMLO
- 100 - ps
t
sk(dif)
differential skew time intra-pair - 5 - ps
CBTL05024 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 March 2014 12 of 21
NXP Semiconductors
CBTL05024
High performance MUX/deMUX switch for Thunderbolt applications
9.4 Control signals characteristics
[1] The leakage current on CA_DET pin must not drive the 1 M pull-down to a HIGH level.
V
I
input voltage LSTX/LSRX to DPMLO+/DPMLO
channel
0.3 - V
DD
+0.3 V
V
IC
common-mode input voltage DP+/DP and DPMLO+/DPMLO 0- V
DD
V
V
ID
differential input voltage DP+/DP to DPMLO+/DPMLO
channel
--1.4 V
I
LIH
HIGH-level input leakage
current
DP+/DP and DPMLO+ pins;
V
DD
=max; V
I
=V
DD
--1 A
DPMLO pins; V
DD
=max; V
I
=V
DD
--5 A
I
LIL
LOW-level input leakage
current
DP+/DP and DPMLO+/DPMLO pins;
V
DD
=max; V
I
=GND
--1 A
Table 14. Channel dynamic and static characteristics
…continued
Symbol Parameter Conditions Min Typ Max Unit
Table 15. CA_DET input buffer characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage 2 - - V
V
IL
LOW-level input voltage - - 0.8 V
I
LI
input leakage current measured with input at V
IH
=V
DD
and V
IL
=0V
[1]
--0.1A
Table 16. HPD input buffer characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage 2 - 5 V
V
IL
LOW-level input voltage - - 0.8 V
Table 17. TB_ENA, DP_PD or AUXIO_EN input characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage CMOS inputs 0.7 V
DD
-- V
V
IL
LOW-level input voltage CMOS inputs - - 0.3 V
DD
V
I
LI
input leakage current measured with input at V
IH
=V
DD
and V
IL
=0V
-110A
Table 18. CA_DETOUT and HPDOUT output buffer characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
OL
LOW-level output voltage I
OL
=2mA; V
DD
=3V 0 - 0.4 V
V
OH
HIGH-level output voltage pull-up voltage; I
OH
= 2mA;
V
DD
=3V
2.5 - - V
t
PD
propagation delay load capacitance C
L
= 5 pF - 50 100 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

CBTL05024BSHP

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Manufacturer:
NXP Semiconductors
Description:
Encoders, Decoders, Multiplexers & Demultiplexers multiplexer demultiplexer
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New from this manufacturer.
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