CBTL05024 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 March 2014 6 of 21
NXP Semiconductors
CBTL05024
High performance MUX/deMUX switch for Thunderbolt applications
5.2 Pin description
Table 3. Pin description
Symbol Pin Type Description
Data path signals
AUX 1 differential I/O AUX differential signals. The input to this pin must
be AC-coupled externally.
AUX+ 2 differential I/O
TB 7 differential I/O Thunderbolt differential signals. These output
signals must be AC-coupled externally.
TB+ 8 differential I/O
AUXIO 23 differential I/O Differential signals for TB MUX.
AUXIO+ 22 differential I/O
DDC_CLK 5 single-ended I/O Pair of single-ended terminals for DDC clock and
data signals.
DDC_DAT 4 single-ended I/O
DP 10 differential I/O High-speed differential pair. The input to this pin
must be AC-coupled externally.
DP+ 11 differential I/O
DPMLO 20 differential I/O Differential signals for DP MUX.
DPMLO+ 19 differential I/O
LSRX 13 single-ended output Single-ended TB low speed receive signal.
LSTX 14 single-ended I/O Single-ended TB low speed transmit signal.
Control signals
HPDOUT 12 CMOS output Output buffer for HPD.
HPD 17 CMOS input HPD input with 5 V tolerance.
CA_DET 18 CMOS input When CA_DET = HIGH, DDC_CLK and DDC_DAT
is selected. When CA_DET = LOW, AUX path is
selected.
CA_DETOUT 16 CMOS output 3.3 V CMOS output buffer for CA_DET.
TB_ENA 15 CMOS input The control input signal to enable Thunderbolt path
for TB MUX.
AUXIO_EN 24 CMOS input The control signal for TB MUX.
DP_PD 6 CMOS input The control signal for DP MUX. This MUX must
work during initial power-up that might have
V
DD
=2.3V.
3.3 V supply option
V
DD
3 Power 3.3 V supply. Pin 3 must be connected to system
power supply.
Ground connections
GND 9, 21 Ground Supply ground (0 V).
GND center
pad
Ground The center pad must be connected to GND plane
for both electrical grounding and thermal relief.
