CBTL05024 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 March 2014 7 of 21
NXP Semiconductors
CBTL05024
High performance MUX/deMUX switch for Thunderbolt applications
6. Functional description
Refer to Figure 1 “Block diagram of CBTL05024.
The following sections describe the individual block functions and capabilities of the
device in more detail.
6.1 Buffer function tables
6.2 AUX MUX function table
6.3 Operation modes of both DPML MUX and TB MUX
[1] HPD must be LOW during Test mode.
Table 4. HPD buffer
HPD input HPDOUT output
00
11
Table 5. CA_DET buffer
CA_DET input CA_DETOUT output
00
11
Table 6. 2 : 1 AUX MUX function
CA_DET input AUXIO
0AUX
1 DDC
Table 7. Operation modes
AUXIO_EN TB_ENA DP_PD CA_DET AUXIO DPMLO Modes R3 R2
0 X 0 X 3-state 3-state DP Standby mode ON ON
0 X 1 X 3-state LS Standby mode ON ON
1 0 0 0 AUX input DP input DP mode ON ON
1 0 0 1 DDC DP input DP++ mode ON ON
1 0 1 X 3-state LS Detect mode ON ON
1 101TBDP inputTest mode
[1]
OFF ON
1 1 0 0 3-state 3-state Sleep mode OFF ON
1 1 1 X TB LS TB mode OFF ON
CBTL05024 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 March 2014 8 of 21
NXP Semiconductors
CBTL05024
High performance MUX/deMUX switch for Thunderbolt applications
7. Limiting values
[1] All voltage values, except differential voltages, are with respect to network ground terminal.
[2] Human Body Model: ANSI/ESDA/JEDEC JDS-001-2012 (Revision of ANSI/ESDA/JEDEC JS-001-2011),
ESDA/JEDEC Joint standard for ESD sensitivity testing, Human Body Model – Component level;
Electrostatic Discharge Association, Rome, NY, USA; JEDEC Solid State Technology Association,
Arlington, VA, USA.
[3] Charged Device Model: JESD22-C101E December 2009 (Revision of JESD22-C101D, October 2008),
standard for ESD sensitivity testing, Charged Device Model – Component level; JEDEC Solid State
Technology Association, Arlington, VA, USA.
8. Recommended operating conditions
[1] During power supply negotiation only a limited supply voltage is available. The control logic and
multiplexers must be in full function with degraded performance. The channel between LSTX/LSRX and
DPMLO+/ must work. The initial R
on
of DP MUX in Table 14 should be < 50 .
Table 8. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage
[1]
0.3 +4.6 V
V
I
input voltage
[1]
0.3 +5.5 V
T
stg
storage temperature 65 +150 C
V
ESD
electrostatic discharge
voltage
HBM
[2]
- 2000 V
CDM
[3]
- 1000 V
Table 9. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
DD
supply voltage 3.3 V supply option 3.0 3.3 3.6 V
initial supply voltage
before power supply
negotiation done
[1]
2.3 - - V
V
I
input voltage CMOS inputs 0.3 - +5.5 V
MUX I/O pins 0.3 - V
DD
+0.3 V
T
amb
ambient temperature operating in free air 20 - +85 C
CBTL05024 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 March 2014 9 of 21
NXP Semiconductors
CBTL05024
High performance MUX/deMUX switch for Thunderbolt applications
9. Characteristics
9.1 Device general characteristics
[1] Do not include current through R4.
[2] Outputs are undefined during reconfiguration, including enable and disable time of the multiplexers.
9.2 3 : 1 TB MUX channel characteristics
Table 10. General characteristics
Symbol Parameter Conditions Min Typ Max Unit
I
DD
supply current
[1]
TB mode; V
DD
= 3.6 V - 0.25 0.35 mA
P
cons
power consumption
[1]
TB mode; V
DD
= 3.6 V; AUXIO_EN = 1,
TB_ENA = 1 and DP_PD = 1
- 0.825 1.26 mW
DP or DP++ modes; AUXIO_EN = 1,
TB_ENA = 0 and DP_PD = 0
- 0.66 1.00 mW
Sleep or DP Standby modes;
(AUXIO_EN = 1, TB_ENA = 1 and
CA_DET = DP_PD = 0) for Sleep mode
or (AUXIO_EN = 0 and DP_PD = 0) for
DP Standby mode
-118W
Detect mode; AUXIO_EN = 1,
TB_ENA = 0 and DP_PD = 1
-118W
Standby mode; AUXIO_EN = 0,
TB_ENA = X and DP_PD = 1
-118W
t
startup
start-up time supply voltage valid to channel specified
operating characteristics
- 100 500 s
t
rcfg
reconfiguration time DP_PD, AUXIO_EN, TB_ENA or
CA_DET state change to channel
specified operating characteristics
[2]
- 50 100 s
Table 11. TB channel of 2 : 1 10G MUX dynamic and static characteristics
Symbol Parameter Conditions Min Typ Max Unit
DDIL differential insertion loss channel is OFF
f=5GHz - 20 - dB
f = 100 MHz - 55 - dB
channel is ON
f=5GHz - 1.3 - dB
f = 100 MHz - 1- dB
DDRL differential return loss f = 5 GHz - 20 - dB
f = 100 MHz - 22 - dB
DDNEXT differential near-end crosstalk adjacent channels are ON
f=5GHz - 18 - dB
f=2.7GHz - 25 - dB
f = 100 MHz - 60 - dB
f=1MHz - 70 - dB
R
on
ON-state resistance V
DD
=3.3V; V
I
=3.3V;
I
I
=5mA
-8.512

CBTL05024BSHP

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Encoders, Decoders, Multiplexers & Demultiplexers multiplexer demultiplexer
Lifecycle:
New from this manufacturer.
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