ISL89166, ISL89167, ISL89168
4
FN7720.2
February 26, 2013
Absolute Maximum Ratings Thermal Information
Supply Voltage, V
DD
Relative to GND. . . . . . . . . . . . . . . . . . . . -0.3V to 18V
Logic Inputs (INA, INB) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to V
DD
+ 0.3V
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to V
DD
+ 0.3V
Average Output Current (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . . . 2000V
Machine Model Class B (Tested per JESD22-A115-A) . . . . . . . . . . . . 200V
Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
Latch-Up
(Tested per JESD-78B; Class 2, Level A)
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
8 Ld TDFN Package (Notes 4, 5). . . . . . . . . 44 3
8 Ld EPSOIC Package (Notes 4, 5). . . . . . . 42 3
Max Power Dissipation at +25°C in Free Air . . . . . . . . . . . . . . . . . . . . . 2.27W
Max Power Dissipation at +25°C with Copper Plane . . . . . . . . . . . . .33.3W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temp Range . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Maximum Recommended Operating
Conditions
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage, V
DD
Relative to GND. . . . . . . . . . . . . . . . . . . . . .4.5V to 16V
Logic Inputs (INA, INB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V
DD
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V
DD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
6. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output
currents of this driver are self limiting by transconductance or r
DS(ON)
and do not required any external components to minimize the peaks. If the
output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to less than the specified
absolute maximum.
DC Electrical Specifications V
DD
= 12V, GND = 0V, No load on OUTA or OUTB, RDTA = RDTB = 0k unless otherwise specified.
Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= +25°C T
J
= -40°C to +125°C
UNITSMIN TYP MAX
MIN
(Note 7)
MAX
(Note 7)
POWER SUPPLY
Voltage Range V
DD
--- 4.5 16 V
V
DD
Quiescent Current I
DD
INx = GND - 5 - - - mA
INA = INB = 1MHz, square wave - 25 - - - mA
UNDERVOLTAGE
VDD Undervoltage Lock-out
(Note 9) (Figure 9)
V
UV
INA = INB = True (Note 10)
-3.3- - -
V
Hysteresis
- ~25 - - -
mV
INPUTs
Input Range for INA, INB V
IN
--- GND V
DD
V
Logic 0 Threshold
for INA, INB
V
IL
Nominally 37% x 3.3V
-1.22- 1.12 1.32 V
Logic 1 Threshold
for INA, INB
V
IH
Nominally 63% x 3.3V
-2.08- 1.98 2.18 V
Input Capacitance of
INA, INB (Note 8)
C
IN
-2- - - pF
ISL89166, ISL89167, ISL89168
5
FN7720.2
February 26, 2013
Input Bias Current
for INA, INB
I
IN
GND < V
IN
< V
DD
--- -10 +10 µA
OUTPUTS
High Level Output Voltage V
OHA
V
OHB
---V
DD
- 0.1 V
DD
V
Low Level Output Voltage
V
OLA
V
OLB
--- GND GND + 0.1 V
Peak Output Source Current I
O
V
O
(initial) = 0V, C
LOAD
= 10nF - -6 - - - A
Peak Output Sink Current I
O
V
O
(initial) = 12V, C
LOAD
= 10nF - +6 - - - A
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
9. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9
10. The true state of a specific part number is defined by the input logic symbol.
AC Electrical Specifications V
DD
= 12V, GND = 0V, No Load on OUTA or OUTB, RDTA = RDTB = 0k unless Otherwise
Specified.
Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
PARAMETERS SYMBOL
TEST CONDITIONS
/NOTES
T
J
= +25°C T
J
= -40°C to +125°C
UNITSMIN TYP MAX
MIN
(Note 7)
MAX
(Note 7)
Output Rise Time (see Figure 4) t
R
C
LOAD
= 10nF,
10% to 90%
-20- - 40 ns
Output Fall Time (see Figure 4) t
F
C
LOAD
= 10nF,
90% to 10%
-20- - 40 ns
Output Rising Edge Propagation Delay (see Figure 3) t
RDLY
RDTx = 0k -25- - 50 ns
Output Falling Edge Propagation Delay (see Figure 3)
(Note 12)
t
FDLY
RDTx = 0k -25- - 50 ns
Rising Propagation Matching (see Figure 3) t
RM
RDTx = 0k - <1ns - - - ns
Falling Propagation Matching (see Figure 3) t
FM
RDTx = 0k - <1ns - - - ns
Rising edge timer delay (Note 11) t
RTDLY20
RTx = 20k,
No load
- 266 - 237 297 ns
t
RTDLY2
RTx = 2.0k, No
load
-42- 29 58 ns
Miller Plateau Sink Current
(See Test Circuit Figure 5)
-I
MP
V
DD
= 10V,
V
MILLER
= 5V
-6- - - A
-I
MP
V
DD
= 10V,
V
MILLER
= 3V
-4.7- - - A
-I
MP
V
DD
= 10V,
V
MILLER
= 2V
-3.7- - - A
DC Electrical Specifications V
DD
= 12V, GND = 0V, No load on OUTA or OUTB, RDTA = RDTB = 0k unless otherwise specified.
Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= +25°C T
J
= -40°C to +125°C
UNITSMIN TYP MAX
MIN
(Note 7)
MAX
(Note 7)
ISL89166, ISL89167, ISL89168
6
FN7720.2
February 26, 2013
Miller Plateau Source Current
(See Test Circuit Figure 6)
I
MP
V
DD
= 10V,
V
MILLER
= 5V
-5.2- - - A
I
MP
V
DD
= 10V,
V
MILLER
= 3V
-5.8- - - A
I
MP
V
DD
= 10V,
V
MILLER
= 2V
-6.9- - - A
NOTE:
11. The rising edge delay timer increases the propagation delay for values of RDTx > 2.0k. Time delays for RDTx < 2.0k and RDTx > 20k are not
specified and are not recommended. The resistors tolerances (including the boundary values of 2.0k and 20.0k) are recommended to be 1% or
better.
12. The falling edge propagation delays are independent of the RDT value.
AC Electrical Specifications V
DD
= 12V, GND = 0V, No Load on OUTA or OUTB, RDTA = RDTB = 0k unless Otherwise
Specified.
Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)
PARAMETERS SYMBOL
TEST CONDITIONS
/NOTES
T
J
= +25°C T
J
= -40°C to +125°C
UNITSMIN TYP MAX
MIN
(Note 7)
MAX
(Note 7)
Test Waveforms and Circuits
FIGURE 3. PROP DELAYS AND MATCHING FIGURE 4. RISE/FALL TIMES
FIGURE 5. MILLER PLATEAU SINK CURRENT TEST CIRCUIT
FIGURE 6. MILLER PLATEAU SOURCE CURRENT TEST CIRCUIT
INA, INB
OUTA
OUTB
0V
3.3V
t
RDLY
t
RDLY
63%
37%
t
FDLY
t
FDLY
t
RM
t
FM
/OUTB
/OUTA
OUTA
OR
OUTB
t
R
t
F
90%
10%
V
MILLER
10V
+I
SENSE
-I
SENSE
10µF
0.1µF
50m
200ns
10k
ISL8916x
10nF

ISL89168FBEAZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 6A PEAK HI SPD PWR MSFT DRVR 8LD EP
Lifecycle:
New from this manufacturer.
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