ISL89166, ISL89167, ISL89168
9
FN7720.2
February 26, 2013
Functional Description
Overview
The ISL89166, ISL89167, ISL89168 drivers incorporate several
features including precision input logic thresholds, undervoltage
lock-out, fast rising high output drive currents and programmable
rising edge output delays.
The programmable delays require only a resistor connecter
between the RDTA or RDTB pins and ground. This is a useful
feature to create dead times for bridge applications to prevent
shoot-through or for synchronous rectifier applications to adjust
the timing.
Fast rising (or falling) output drive current of the ISL89166,
ISL89167, ISL89168 minimizes the turn-on (off) delay due to the
input capacitance of the driven FET. The switching transition
period at the Miller plateau is also minimized by the high drive
currents. (See the specified Miller plateau currents in the AC
Electrical Specifications on page 5).
The start-up sequence for is designed to prevent unexpected
glitches when V
DD
is being turned on or turned off. When
V
DD
< ~1V, an internal 10k resistor connected between the
output and ground, help to keep the gate voltage close to ground.
When ~1V<V
DD
< UV, both outputs are driven low while ignoring
the logic inputs. This low state has the same current sinking
capacity as during normal operation. This insures that the driven
FETs are held off even if there is a switching voltage on the drains
that can inject charge into the gates via the Miller capacitance.
When V
DD
> UVLO, and after a 400µs delay, the outputs now
respond to the logic inputs. See Figure 9 for complete details.
For the negative transition of V
DD
through the UV lockout voltage,
the outputs are active low when V
DD
< ~3.2V
DC
regardless of the
input logic states.
Application Information
Programming Rising Edge Delays
As compared to setting the output delays of a driver using an
resistor, capacitor and diode on the logic inputs, programming
the rising edge output delays of the ISL89166, ISL89167,
ISL89168 is almost trivial.
All that is necessary is to select the required resistor value from
the Propagation Delay vs RDT graph, Figure 17. Unlike using an
RCD network, the operating tolerances over temperature are
specified. If a traditional RCD network (Figure 19) is used on the
input logic, then it is necessary to account for the tolerance of the
logic input threshold, the tolerances of R and C, and their
temperature sensitivity.
Paralleling Outputs to Double the Peak Drive
Currents
The typical propagation matching of the ISL89166 and ISL89167
is less than 1ns. Note that the propagation matching is only valid
when RTDA and RTDB = 0k. The matching is so precise that
carefully matched and calibrated scopes probes and scope
channels must be used to make this measurement. Because of
this excellent performance, these driver outputs can be safely
paralleled to double the current drive capacity. It is important
that the INA and INB inputs be connected together on the PCB
with the shortest possible trace. This is also required of OUTA and
OUTB. Note that the ISL89168 cannot be paralleled because of
the complementary logic.
Power Dissipation of the Driver
The power dissipation of the ISL89166, ISL89167, ISL89168 is
dominated by the losses associated with the gate charge of the
driven bridge FETs and the switching frequency. The internal bias
current also contributes to the total dissipation but is usually not
significant as compared to the gate charge losses.
Figure 20 illustrates how the gate charge varies with the gate
voltage in a typical power MOSFET. In this example, the total gate
charge for V
gs
= 10V is 21.5nC when V
DS
= 40V. This is the
charge that a driver must source to turn-on the MOSFET and
must sink to turn-off the MOSFET.
Equation 1 shows calculating the power dissipation of the driver:
FIGURE 18. SETTING DELAYS WITH A RESISTOR
FIGURE 19. SETTING DELAYS WITH A RCD NETWORK
INx
R
del
c
del
D
OUTx
ISL89160
Q
g,
GATE CHARGE (nC)
12
10
8
6
4
2
0
024681012141618202224
V
gs
GATE-SOURCE VOLTAGE (V)
FIGURE 20. MOSFET GATE CHARGE vs GATE VOLTAGE
V
DS
= 64V
V
DS
= 40V
(EQ. 1)
P
D
2Q
c
freq V
GS
R
gate
R
gate
r
DS ON
+
------------------------------------------
I
DD
freqV
DD
+=
