.....................Document #: 001-05103 Rev *B Page 14 of 27
CLK_REQ[1:9]# Deassertion (CLKREQ# -> HIGH)
The impact of deasserting the CLKREQ# pins is that all SRC
outputs that are set in the control registers to stoppable via
deassertion of CLKREQ# are to be stopped after their next
transition. The final state of all stopped SRC clocks is
Low/Low.
PD (Power-down) Clarification
The CK_PWRGD/PD# pin is a dual-function pin. During initial
power-up, the pin functions as CK_PWRGD. Once
CK_PWRGD has been sampled HIGH by the clock chip, the
pin assumes PD# functionality. The PD# pin is an
asynchronous active LOW input used to shut off all clocks
cleanly prior to shutting off power to the device. This signal is
synchronized internal to the device prior to powering down the
clock synthesizer. PD# is also an asynchronous input for
powering up the system. When PD# is asserted LOW, all
clocks need to be driven to a LOW value and held prior to
turning off the VCOs and the crystal oscillator.
PD (Power-down) Assertion
When PD# is sampled LOW by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must be
held HIGH or tri-stated (depending on the state of the control
register drive mode bit) on the next diff clock# HIGH-to-LOW
transition within 4 clock periods. When the SMBus PD drive
mode bit corresponding to the differential (CPU, SRC, and
DOT) clock output of interest is programmed to ‘0’, the clock
outputs are held with “Diff clock” pin driven HIGH, and “Diff
clock#” tri-state. If the control register PD drive mode bit corre-
sponding to the output of interest is programmed to “1”, then
both the “Diff clock” and the “Diff clock#” are tri-state. Note that
Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for
all differential outputs. This diagram and description is appli-
cable to valid CPU frequencies 100, 133, 166, and 200 MHz.
In the event that PD mode is desired as the initial power-on
state, PD must be asserted HIGH in less than 10 s after
asserting CK_PWRGD. It should be noted that 96_100_SSC
will follow the DOT waveform when selected for 96 MHz and
the SRC waveform when in 100-MHz mode.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up. It should be noted that 96_100_SSC will
follow the DOT waveform when selected for 96 MHz and the
SRC waveform when in 100-MHz mode.
Figure 3. CLK_REQ#[1:9] Deassertion/Assertion Waveform
Figure 4. Power-down Assertion Timing Waveform
PD#
USB, 48MHz
DOT96T
DOT96C
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
