SL28647BLCT Datasheet SL28647CLCT, SL28647BLCT, SL28647BLC | P4-P6

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Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 3.

The block write and block read protocol is outlined in Table 4

while Table 5 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h)

Table 2. Frequency Select Table FSA, FSB, and FSC

FSC FSB FSA CPU SRC PCIF/PCI 27MHz REF DOT96 USB

000266 MHz

100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz

101100 MHz

001133 MHz

011166 MHz

010200 MHz

100333 MHz

110400 MHz

111 Reserved

Table 3. Command Code Definition

Bit Description

7 0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Table 4. Block Read and Block Write Protocol

Block Write Protocol Block Read Protocol

Bit Description Bit Description

1Start 1Start

8:2 Slave address–7 bits 8:2 Slave address–7 bits

9 Write 9 Write

10 Acknowledge from slave 10 Acknowledge from slave

18:11 Command Code–8 bits 18:11 Command Code–8 bits

19 Acknowledge from slave 19 Acknowledge from slave

27:20 Byte Count–8 bits

(Skip this step if I

C_EN bit set)

20 Repeat start

28 Acknowledge from slave 27:21 Slave address–7 bits

36:29 Data byte 1–8 bits 28 Read = 1

37 Acknowledge from slave 29 Acknowledge from slave

45:38 Data byte 2–8 bits 37:30 Byte Count from slave–8 bits

46 Acknowledge from slave 38 Acknowledge

.... Data Byte/Slave Acknowledges 46:39 Data byte 1 from slave–8 bits

.... Data Byte N–8 bits 47 Acknowledge

.... Acknowledge from slave 55:48 Data byte 2 from slave–8 bits

.... Stop 56 Acknowledge

.... Data bytes from slave/Acknowledge

.... Data Byte N from slave–8 bits

.... NOT Acknowledge

.... Stop

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Table 5. Byte Read and Byte Write Protocol

Byte Write Protocol Byte Read Protocol

Bit Description Bit Description

1Start 1Start

8:2 Slave address–7 bits 8:2 Slave address–7 bits

9Write 9Write

10 Acknowledge from slave 10 Acknowledge from slave

18:11 Command Code–8 bits 18:11 Command Code–8 bits

19 Acknowledge from slave 19 Acknowledge from slave

27:20 Data byte–8 bits 20 Repeated start

28 Acknowledge from slave 27:21 Slave address–7 bits

29 Stop 28 Read

29 Acknowledge from slave

37:30 Data from slave–8 bits

38 NOT Acknowledge

39 Stop

Control Registers

Byte 0 Control Register 0

Bit @Pup Name Description

7 0 RESEREVD RESERVED

6 0 RESEREVD RESERVED

5 0 RESEREVD RESERVED

4 0 iAMT_EN Set via SMBus or by combination of PD, CPU_STP and PCI_STP

0 = Legacy mode, 1 = iAMT enable

3 0 RESEREVD RESERVED

2 0 RESEREVD RESERVED

1 0 RESEREVD RESERVED

0 1 PD_Restore Save configuration when PD# is asserted

0 = Config. cleared, 1 = Config. saved

Byte 1 Control Register 1

Bit @Pup Name Description

7 1 SRC7_OE SRC7 Output Enable

0 = Disabled, 1 = Enabled

6 1 SRC6_OE SRC[6 Output Enable

0 = Disabled, 1 = Enabled

5 1 SRC5_OE SRC5 Output Enable

0 = Disabled, 1 = Enabled

4 1 SRC4_OE SRC4 Output Enable

0 = Disabled, 1 = Enabled

3 1 SRC3_OE SRC3 Output Enable

0 = Disabled, 1 = Enabled

2 1 SRC2_OE SRC2 Output Enable

0 = Disabled, 1 = Enabled

1 1 SRC1_OE SRC1 Output Enable

0 = Disabled, 1 = Enabled

0 1 SRC0

/LCD_96/100M_OE

SRC0/LCD_96/100M Output Enable

0 = Disabled, 1 = Enabled

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Byte 2 Control Register 2

Bit @Pup Name Description

7 1 PCIF0_OE PCIF0 Output Enable

0 = Disabled, 1 = Enabled

6 1 27M_non_SS/DOT_96_OE 27M Non-spread and DOT_96 MHz Output Enable

0 = Disable, 1 = Enabled

5 1 48M_OE 48-MHz Output Enable

0 = Disabled, 1 = Enabled

4 1 REF0_OE REF0 Output Enable

0 = Disabled, 1 = Enabled

3 1 REF1_OE REF1 Output Enable

0 = Disabled, 1 = Enabled

2 1 CPU1_OE CPU[T/C]1 Output Enable

0 = Disabled, 1 = Enabled

1 1 CPU0_OE CPU[T/C]0 Output Enable

0 = Disabled, 1 = Enabled

0 1 CPU, SRC, PCI, PCIF

Spread Enable

PLL1 (CPU PLL) Spread Spectrum Enable

0 = Spread off, 1 = Spread on

Byte 3 Control Register 3

Bit @Pup Name Description

7 1 PCI4_OE PCI4 Output Enable

0 = Disabled, 1 = Enabled

6 1 PCI3_OE PCI3 Output Enable

0 = Disabled, 1 = Enabled

5 1 PCI2_OE PCI2 Output Enable

0 = Disabled, 1 = Enabled

4 1 PCI1_OE PCI1 Output Enable

0 = Disabled, 1 = Enabled

3 1 RESERVED RESERVED

2 1 RESERVED RESERVED

1 1 CPU2/SRC10_OE CPU2/SRC10 Output Enable

0 = Disabled, 1 = Enabled

0 1 RESERVED RESERVED

Byte 4 Control Register 4

Bit @Pup Name Description

7 0 SRC7_STP_CTRL Allow control of SRC7 with assertion of PCI_STP# or SW PCI_STP