7©2015 Integrated Device Technology, Inc December 7, 2015
840004-11 Datasheet
Parameter Measurement Information
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
Output Skew
Output Duty Cycle Pulse Width/Period
RMS Phase Jitter
Output Rise/Fall Time
SCOPE
Qx
GND
V
DD,
1.65V±5%
-1.65V±5%
V
DDO
V
DDA
1.65V±5%
t
sk(o)
V
DDO
2
V
DDO
2
Qx
Qy
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
Q0:Q3
20%
80%
80%
20%
t
R
t
F
Q0:Q3
8©2015 Integrated Device Technology, Inc December 7, 2015
840004-11 Datasheet
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Outputs:
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. We recommend
that there is no trace attached.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 840004-11 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
DD,
V
DDA
and V
DDO
should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V
DD
pin and also shows that V
DDA
requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the V
DDA
pin.
Figure 1. Power Supply Filtering
V
DD
V
DDA
3.3V
10Ω
10µF.01µF
.01µF
9©2015 Integrated Device Technology, Inc December 7, 2015
840004-11 Datasheet
Crystal Input Interface
The 840004-11 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 25MHz, 18pF parallel resonant crystal and were
chosen to minimize the ppm error.
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 applications, R1 and R2
can be 100. This can also be accomplished by removing R1 and
making R2 50. By overdriving the crystal oscillator, the device will
be functional, but note, the device performance is guaranteed by
using a quartz crystal.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
22pF
C2
22pF
XTAL_IN
XTAL_OUT
Ro Rs
Zo = Ro + Rs
50
Ω
0.1µf
R1
R2
V
CC
V
CC

840004AG-11LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 4 LVCMOS OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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