1. General description
The ADC0808S is a differential, high-speed, 8-bit Analog-to-Digital Converter (ADC)
optimized for telecommunication transmission control systems and tape drive
applications. It allows signal sampling frequencies up to 250 MHz.
The ADC0808S clock inputs are selectable between 1.8 V Complementary Metal Oxide
Semiconductor (CMOS) or Low-Voltage Differential Signals (LVDS). The data output
signal levels are 1.8 V CMOS.
All static digital inputs (CLKSEL, CCSSEL, CE_N, OTC, DEL0 and DEL1) are 1.8 V
CMOS compatible.
The ADC0808S offers the most flexible acquisition control system possible due to its
programmable Complete Conversion Signal (CCS) which allows the delay time of the
acquisition clock and acquisition clock frequency to be adjusted.
The ADC0808S is supplied in an HTQFP48 package.
2. Features
n 8-bit resolution
n High-speed sampling rate up to 250 MHz
n Maximum analog input frequency up to 560 MHz
n Programmable acquisition output clock (complete conversion signal)
n Differential analog input
n Integrated voltage regulator or external control for analog input full-scale
n Integrated voltage regulator for input common-mode reference
n Selectable 1.8 V CMOS or LVDS clock input
n 1.8 V CMOS digital outputs
n 1.8 V CMOS compatible static digital inputs
n Binary or 2’s complement CMOS outputs
n Only 2 clock cycles latency
n Industrial temperature range from 40 °Cto+85°C
n HTQFP48 package
3. Applications
n 2.5G and 3G cellular base infrastructure radio transceivers
n Wireless access systems
n Fixed telecommunications
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
Rev. 03 — 24 February 2009 Product data sheet
ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 24 February 2009 2 of 23
NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
n Optical networking
n Wireless Local Area Network (WLAN) infrastructure
n Tape drive applications
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number Sampling frequency
(MHz)
Package
Name Description Version
ADC0808S125HW/C1 125 HTQFP48 plastic thermal enhanced thin quad flat package;
48 leads; body 7 × 7 × 1 mm; exposed die pad
SOT545-2
ADC0808S250HW/C1 250
Fig 1. Block diagram
8 8
001aai267
TRACK
AND
HOLD
ADC
CORE
LATCH
LATCH
RESISTOR
LADDERS
CLOCK DRIVER
OUTPUTS
ENABLE
CMADC
REFERENCE
INTERNAL
REFERENCE
ADC0808S
U/I
INN
IN
DEL0
DEL1
CCS
17
39
38
1929
33
32
30
FSIN/
REFSEL
3736
40
26
21
20
CCSSEL
D0 to D7
OTC
IR
CMADC
CLKSEL
CLK+ CLK
CE_N
LATCH
ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 24 February 2009 3 of 23
NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration
ADC0808S
OGND1 CLKSEL
D3 i.c.
i.c. V
CCA1(3V3)
V
CCO1(1V8)
IN
D4 INN
i.c. AGND2
OGND2 FSIN/REFSEL
D5 CMADC
i.c. AGND1
DGND
V
CCO2(1V8)
NC1V8
D6 CCSSEL
i.c. n.c.
V
CCO3(1V8)
i.c.
D7 D2
i.c. OGND4
OGND3 i.c.
CCS D1
i.c. V
CCO4(1V8)
CE_N i.c.
IR D0
OTC DEL1
DGND1 DEL0
V
CCD1(1V8)
n.c.
CLK
CLK+
001aai268
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
37
24
Table 2. Pin description
Symbol Pin Type
[1]
Description
OGND1 1 G data output ground 1
D3 2 O data output bit 3
i.c. 3 - internally connected; leave open
V
CCO1(1V8)
4 P data output supply voltage 1 (1.8 V)
D4 5 O data output bit 4
i.c. 6 - internally connected; leave open
OGND2 7 G data output ground 2
D5 8 O data output bit 5
i.c. 9 - internally connected; leave open
V
CCO2(1V8)
10 P data output supply voltage 2 (1.8 V)
D6 11 O data output bit 6
i.c. 12 - internally connected; leave open
V
CCO3(1V8)
13 P data output supply voltage 3 (1.8 V)
D7 14 O data output bit 7

ADC0808S125/DB

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
BOARD EVALUATION FOR ADC0808S125
Lifecycle:
New from this manufacturer.
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