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ADC0808S125/DB

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ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 24 February 2009 10 of 23
NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
8. Limiting values
9. Thermal characteristics
[1] In compliance with JEDEC test board, in free air.
10. Static characteristics
Table 10. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CCA
analog supply voltage −0.5 +4.6 V
V
CCD
digital supply voltage −0.5 +2.5 V
V
CCO
output supply voltage −0.5 +2.5 V
V
i(IN)
input voltage on pin IN referenced to AGND −0.5 V
CCA
+1 V
V
i(INN)
input voltage on pin INN referenced to AGND −0.5 V
CCA
+1 V
V
i(CLK)
input voltage on pin CLK referenced to DGND −0.5 V
CCD
+ 0.55 V
T
stg
storage temperature −55 +150 °C
T
amb
ambient temperature −40 +85 °C
T
j
junction temperature - 150 °C
Table 11. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction to ambient
[1]
36.2 K/W
R
th(j-c)
thermal resistance from junction to case
[1]
14.3 K/W
Table 12. Static characteristics
V
CCA
= 3.0 V to 3.6 V; V
CCD
= 1.65 V to 1.95 V; V
CCO
= 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together;
T
amb
=
−
40
°
C to +85
°
C; V
i(IN)
−
V
i(INN)
= 2.0 V
−
0.5 dB; V
I(cm)
= 0.95 V; V
FSIN
= 0 V; typical values are measured at
V
CCA
= 3.3 V, V
CCD
=V
CCO
= 1.8 V, T
amb
=25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
CCA
analog supply voltage 3.0 3.3 3.6 V
V
CCD
digital supply voltage 1.65 1.80 1.95 V
V
CCO
output supply voltage 1.65 1.80 1.95 V
I
CCA
analog supply current f
clk
= 125 MHz; f
i
= 1.25 MHz - 60 - mA
I
CCD
digital supply current f
clk
= 125 MHz; f
i
= 1.25 MHz - 12 - mA
I
CCO
output supply current f
clk
= 125 MHz; f
i
= 1.25 MHz - 11 - mA
P
tot
total power dissipation f
clk
= 125 MHz; f
i
= 1.25 MHz - 240 - mW
Clock inputs: pins CLK+ and CLK−
R
i
input resistance
[1]
-10-kΩ
C
i
input capacitance
[1]
-1-pF
LVDS clock input; see
Figure 3
∆V
I
input voltage range V
I
on pin CLK+ or CLK−;
|V
gpd
|<50mV
[2]
825 - 1575 mV
ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 24 February 2009 11 of 23
NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
[1] Guaranteed by design.
[2] |V
gpd
| is the voltage of ground potential difference across or between boards.
[3] The ADC input range can be adjusted with an external reference voltage applied to pin FSIN. This voltage must be referenced to AGND.
V
idth
input differential threshold voltage |V
gpd
| < 50 mV
[2]
−100 - +100 mV
I
I
input current 825 mV < V
I
< 1575 mV - - 50 µA
1.8 V CMOS clock input; see
Figure 4
V
IL
LOW-level input voltage DGND - 0.2V
CCD
V
V
IH
HIGH-level input voltage 0.8V
CCD
-V
CCD
V
I
IL
LOW-level input current V
IL
= 0.2V
CCD
--50µA
I
IH
HIGH-level input current V
IH
= 0.8V
CCD
--50µA
Analog inputs: pins IN and INN
R
i
input resistance
[1]
- 1.0 - MΩ
C
i
input capacitance
[1]
- 1.0 - pF
V
I(cm)
common-mode input voltage V
i(IN)
=V
i(INN)
;
output code = 127
0.7 0.95 1.0 V
Digital input pins: OTC, CE_N, DEL0, DEL1, CLKSEL and CCSSEL
V
IL
LOW-level input voltage DGND - 0.2V
CCD
V
V
IH
HIGH-level input voltage 0.8V
CCD
-V
CCD
V
I
IL
LOW-level input current V
IL
= 0.3V
CCD
--50µA
I
IH
HIGH-level input current V
IH
= 0.7V
CCD
--50µA
Voltage controlled regulator output: pin CMADC
V
O(cm)
common-mode output voltage 0.85 0.95 1.1 V
Reference voltage input: pin FSIN
[3]
V
FSIN
voltage on pin FSIN internal reference - 0 0.6 V
external reference 1.15 1.25 1.35 V
I
i(FSIN)
input current on pin FSIN - 12 - µA
V
i(p-p)(max)
maximum peak-to-peak input
voltage
internal reference 1.92 2 2.03 V
external reference
V
FSIN
= 1.15 V 1.80 1.825 1.85 V
V
FSIN
= 1.25 V 1.98 1.99 2.03 V
V
FSIN
= 1.35 V 2.11 2.16 2.18 V
Digital outputs: pins D0 to D7, CCS and IR
V
OL
LOW-level output voltage OGND - 0.2 V
V
OH
HIGH-level output voltage V
CCO
− 0.2 - V
CCO
V
Table 12. Static characteristics
…continued
V
CCA
= 3.0 V to 3.6 V; V
CCD
= 1.65 V to 1.95 V; V
CCO
= 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together;
T
amb
=
−
40
°
C to +85
°
C; V
i(IN)
−
V
i(INN)
= 2.0 V
−
0.5 dB; V
I(cm)
= 0.95 V; V
FSIN
= 0 V; typical values are measured at
V
CCA
= 3.3 V, V
CCD
=V
CCO
= 1.8 V, T
amb
=25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 24 February 2009 12 of 23
NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
11. Dynamic characteristics
Table 13. Dynamic characteristics
V
CCA
= 3.0 V to 3.6 V; V
CCD
= 1.65 V to 1.95 V; V
CCO
= 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together;
T
amb
=
−
40
°
C to +85
°
C; V
i(IN)
−
V
i(INN)
= 2.0 V
−
0.5 dB; V
I(cm)
= 0.95 V; V
FSIN
= 0 V; typical values are measured at
V
CCA
= 3.3 V, V
CCD
=V
CCO
= 1.8 V, T
amb
=25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock timing input: pins CLK+ and CLK−
f
clk(min)
minimum clock frequency - - 1 MHz
f
clk(max)
maximum clock frequency 250 - - MHz
t
w(clk)
clock pulse width f
clk
= 125 MHz 1.8 - - ns
Timing output: pins D0 to D7 and IR
[1]
; see Figure 5
t
d(s)
sampling delay time 1.8 V CMOS clock - 1.3 - ns
LVDS clock - 1.65 - ns
t
h(o)
output hold time 1.8 V CMOS clock 3.3 4.4 - ns
LVDS clock 4.2 4.8 - ns
t
d(o)
output delay time 1.8 V CMOS clock - 5.4 6.9 ns
LVDS clock - 5.8 7.3 ns
Timing complete conversion signal: pin CCS; see
Figure 6
f
CCS(max)
maximum CCS frequency 125 - - MHz
t
d(CCS)
CCS delay time DEL0 = HIGH; DEL1 = LOW - 0.3 - ns
DEL0 = LOW; DEL1 = HIGH - 0.8 - ns
DEL0 = HIGH; DEL1 = HIGH - 1.9 - ns
3-state output delay time: pins CCS, IR and D7 to D0
t
dZH
float to active HIGH delay time - 2.1 - ns
t
dZL
float to active LOW delay time - 2.2 - ns
t
dHZ
active HIGH to float delay time - 3.3 - ns
t
dLZ
active LOW to float delay time - 2.9 - ns
Analog signal processing (50 % clock duty factor); see
Section 12
INL integral non-linearity f
clk
= 20 MHz; f
i
= 21.4 MHz - ±0.82 - LSB
DNL differential non-linearity f
clk
= 20 MHz; f
i
= 21.4 MHz; no
missing code guaranteed
- ±0.4 - LSB
E
O
offset error V
CCA
= 3.3 V; V
CCD
= 1.8 V;
T
amb
=25°C; output code = 127
- 2.5 - mV
E
G
gain error spread from device to device;
V
CCA
= 3.3 V; V
CCD
= 1.8 V;
T
amb
=25°C
- 1.85 - %
B bandwidth f
clk
= 125 MHz; −3 dB; full-scale
input
[2]
- 560 - MHz
THD total harmonic distortion f
clk
= 125 MHz; f
i
=78MHz
[3]
- −53 - dB
f
clk
= 250 MHz; f
i
= 125 MHz - −53 - dB
N
th(RMS)
RMS thermal noise shorted input; f
clk
= 125 MHz - 0.5 - LSB
S/N signal-to-noise ratio f
clk
= 125 MHz; f
i
=78MHz
[4]
- 48 - dBc
f
clk
= 250 MHz; f
i
= 125 MHz - 47 - dBc
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ADC0808S125/DB

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